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PDF RTL8201BL-LF Data sheet ( Hoja de datos )
| Número de pieza | RTL8201BL-LF | |
| Descripción | SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER | |
| Fabricantes | REALTEK | |
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RTL8201BL
RTL8201BL-LF
SINGLE CHIP SINGLE PORT 10/100M FAST
ETHERNET PHYCEIVER
DATASHEET
Rev. 1.3
26 July 2005
Track ID: JATR-1076-21
1 page  
RTL8201BL
Datasheet
1. Introduction
The RTL8201BL is a single-port Phyceiver with an MII (Media Independent
Interface)/SNI(Serial Network Interface). It implements all 10/100M Ethernet
Physical-layer functions including the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD),
10Base-Tx Encoder/Decoder and Twisted Pair Media Access Unit (TPMAU).
A PECL interface is supported to connect with an external 100Base-FX fiber optical
transceiver. The chip is fabricated with an advanced CMOS process to meet low voltage
and low power requirements.
The RTL8201BL can be used in a NIC, MAU, CNR, ACR, Ethernet Hub, or Ethernet
Switch. Additionally, it can be used in any embedded system with an Ethernet MAC that
needs a twisted pair physical connection or fiber PECL interface to an external
100Base-FX optical transceiver module.
2. System Applications
LOC (LAN on Chipset)
NIC (Network Interface Card)
MAU (Media Attachment Unit)
CNR (Communication and Networking Riser)
ACR (Advanced Communication Riser)
Ethernet Hub, Ethernet Switch
Single Chip Single Port 10/100M Fast Ethernet Phyceiver
1
Track ID: JATR-1076-21 Rev. 1.3
5 Page 
RTL8201BL
Datasheet
6.6. LED Interface/PHY Address Config
These five pins are latched into the RTL8201BL during power up reset to configure PHY address [0:4] used for MII
management register interface. And then, in normal operation after initial reset, they are used as driving pins for status
indication LED. The driving polarity, active low or active high, is determined by each latched status of the PHY address [4:0]
during power-up reset. If latched status is High then it will be active low, and if latched status is Low then it will be active high.
Refer to Section 7.5 for more information.
Symbol
PHYAD0/
LED0
PAD1/
LED1
PHYAD2/
LED2
PHYAD3/
LED3
PHYAD4/
LED4
Type
LI/O
LI/O
LI/O
LI/O
LI/O
Pin No.
9
10
12
13
15
Description
PHY Address [0]
Link LED: Active when linked.
PHY Address [1]
Full Duplex LED: Active when in Full Duplex operation.
PHY Address [2]
Link 10/ACT LED: Active when linked in 10Base-T mode, and blinking
when transmitting or receiving data.
PHY Address [3]
Link 100/ACT LED: Active when linked in 100Base-TX and blinking
when transmitting or receiving data.
PHY Address [4]
Collision LED: Active when collisions occur.
6.7. Reset and Other Pins
Symbol
RESETB
PWFBOUT
Type
I
O
PWFBIN
NC
I
Pin No.
42
32
8
27
Description
RESETB: Set low to reset the chip. For a complete reset function, this pin
must be asserted low for at least 10ms.
Power Feedback Output: Be sure to connect a 22uF tantalum capacitor for
frequency compensation and a 0.1uF capacitor for noise de-coupling. Then
connect this pin through a ferrite bead to PWFBIN(pin8). The connection
method is figured in section 7.11.
Power Feedback Input: see the description of PWFBOUT.
Not connection
6.8. Power and Ground Pins
Symbol
AVDD33
AGND
DVDD33
DGND
Type
P
P
P
P
Pin No.
36
29,35
14,48
11,17,45
Description
3.3V Analog power input: 3.3V power supply for analog circuit; should be
well decoupled.
Analog Ground: Should be connected to a larger GND plane
3.3V Digital Power input: 3.3V power supply for digital circuit.
Digital Ground: Should be connected to a larger GND plane.
Single Chip Single Port 10/100M Fast Ethernet Phyceiver
7
Track ID: JATR-1076-21 Rev. 1.3
11 Page | ||
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| PDF Descargar | [ Datasheet RTL8201BL-LF.PDF ] | |
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