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PDF HMS91C8132 Data sheet ( Hoja de datos )
| Número de pieza | HMS91C8132 | |
| Descripción | 8-BIT SINGLE-CHIP MICROCONTROLLERS | |
| Fabricantes | MagnaChip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HMS91C8132 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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MAGNACHIP SEMICONDUCTOR LTD.
8-BIT SINGLE-CHIP MICROCONTROLLERS
HMS91C8132
HMS97C8132
User’s Manual (Ver. 1.6)
1 page  
HMS91C8132/97C8132
1.3 Features
Item
Features
ROM
32K x 8-bit
RAM
1K x 8-bit
Instruction Cycle
Instruction Set
With variable instruction execution time function
1.66µs / 3.33µs / 26.6µs (with main system clock : 7.2MHz)
366.2µs (with sub-system clock : 32.768KHz)
MCS-51 Micro-controller Compatible Instruction Set
I/O Port
CMOS I/O : 62 pins (including 4-open drain ports)
Power fail
detector
Detection voltage 2.8V,1.8V - Reset is generated when power fail detection is enabled.
level
4.5V, 3.0V - A flag is set when power fail detection is enabled.
A/D Converter
8-bit resolution x 8-channels
Serial Interface
3-wire serial I/O mode : 2 channels
Full duplex UART : 1 channel
Timer/Counter
Six 16-bit timers/event counters
Dedicated Watchdog timer
Buzzer(Beep) Output
1.2KHz (fx/6000), 2.4KHz (fx/3000), 4.5KHz (fx/1600), 8.0KHz (fx/900)
Interrupt Source
7 External, 11 Internal Sources
PLL
Frequency
Synthesizer
Division Mode
Direct division mode (VCOL pin)
Pulse swallow mode (VCOH and VCOL pins)
Reference
Frequency
13 types selected by program
1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, 50KHz
Charge Pump Error out : EO pin
Phase Detector Unlock detectable by program
Frequency Counter
Frequency Measurement
AMIFC pin : for 450KHz count
FMIFC pin : for 10.7MHz count
Standby Function
Idle mode
Power-down mode
Reset
Reset by RESET pin, The reset is active high level.
When the MCU operating, the reset is low level
Reset by Vdet circuit
Vdet circuit: Detection of less than 2.7V (Normal operation mode)
Power Supply Voltage
VDD = 3 to 5.5V (with PLL operating)
VDD > 1.8V (Data retention mode)
System Clock
Main system clock : 7.2MHz
Sub-system clock : 32.768KHz
Package
80 pin plastic MQFP
2 DEC. 2004 Ver 1.6
5 Page 
HMS91C8132/97C8132
7FH 7FH
Bank
Select
Bits
in PSW
2FH
20H
11
18H
10
10H
01 08H
1FH
17H
0FH
07H
0
Page 0
Bit-Addressable
Space
(Bit Addresses 0-7F)
4 Banks of
8 Registers
R0-R7
Reset Value of
Stack Pointer
Bank
Select
Bits
in PSW
2FH
20H
11
18H
10
10H
01 08H
1FH
17H
0FH
07H
0
Page 6
Bit-Addressable
Space
(Bit Addresses 0-7F)
4 Banks of
8 Registers
R0-R7
Reset Value of
Stack Pointer
Figure 2-6 Page0 ~ Page6 of Internal RAM
When the DTS_MODE bit of CPUMD SFR is set to HIGH,
the internal 1K RAM can be accessed by the page scheme
which is similar to HMS9XC8032 or MOVX instruction. In
the page scheme, the only different point from HMS9XC8032
is that WRPG SFR is ignored and RDPG SFR determines
both of write page and read page. Figure 2-7 shows the data
memory address space. User can access the memory area
from page1 to page6 with movx instructions. Figure 2-7 also
shows the address relation between movx instruction and the
page scheme. For example, addresses 103h,27F of movx in-
struction correspond to address 3h of page 3 and 7Fh of page
5, respectively. If the operand address of movx instruction is
greater than 2FFh, it is wrap arounded with the following
equation
address = address % 300h
The value of DPTR determines the operand address of
MOVX DPTR type instruction. In MOVX ri type instruction
R0 or R1 determines the lower 8 bits of operand address and
the least significant 2 bits of port 2 output register(P2DATA
SFR) determine the MSB 2 bits.
8 DEC. 2004 Ver 1.6
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HMS91C8132.PDF ] | |
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