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PDF MT6253 Data sheet ( Hoja de datos )
| Número de pieza | MT6253 | |
| Descripción | GSM/GPRS Baseband Process | |
| Fabricantes | MediaTek | |
| Logotipo |  |
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MT6253 GSM/GPRS Baseband
Process Data Sheet
Version:
Release date:
0.99 SP1
2009-07-30
© 2009 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Specifications are subject to change without notice.
1 page  
MT6253
GSM/GPRS Baseband Process Data Sheet
v0.99 SP1 Confidential A
Preface
Acronym for Register Type
R/W
RO
RC
WO
W1S
W1C
Capable of both read and write access
Read only
Read only. After reading the register bank, each bit which is HIGH(1) will be cleared to LOW(0 )
automatically.
Write only
Write only. When writing data bits to register bank, each bit which is HIGH(1) will cause the
corresponding bit to be set to 1. Data bits which are LOW(0) has no effect on the corresponding bit.
Write only. When writing data bits to register bank, each bit which is HIGH(1) will cause the
corresponding bit to be cleared to 0. Data bits which are LOW(0) has no effect on the corresponding bit.
MediaTek Confidential
© 2009 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 5 of 643
5 Page 
MT6253
GSM/GPRS Baseband Process Data Sheet
v0.99 SP1 Confidential A
Supports SDIO interface for SDIO peripherals as
well as WIFI connectivity
DAI/PCM and I2S interface for Audio
application
Low Power Schemes
Power Down Mode for analog and digital
circuits
Processor Sleep Mode
Over Voltage Protection
Test and Debug
Built-in digital and analog loop back modes for
both Audio and Baseband Front-End
DAI port complying with GSM Rec.11.10
JTAG port for debugging embedded MCU
1.2 MODEM Features
Pause Mode of 32KHz clocking at Standby State
Integrated RF Receiver
3-channel Auxiliary 10-bit A/D Converter for
application usage other than battery monitoring
Power and Supply Management
2.8V to 4.7V Input Range
Charger Input up to 8V
11 sets of LDO Optimized for Specific GSM
Sub-systems
Direct conversion architecture
Quad band differential input LNAs
Quadrature RF mixers
Fully integrated channel filter with f3dB=150kHz
95 dB gain with 60 dB gain control range
No IIP2 calibration
One LDO for RF transceiver
High Operation Efficiency and Low Stand-by
Current
Li-Ion Battery Charge function
Dual SIM Card Interface
One boost regulator and Four Open-Drain
Output Current Regulators to Supply/Control the
LED
LDO type Vibrator
One NMOS switch to control R(GB) LED
Thermal Overload Protection
Under Voltage Lock-out Protection
Integrated RF Transmitter
Offset phase lock loop
IQ modulator DC offset calibration by BB
ADC/DAC.
Precise quadrature by IF divide-by-4.
Integrated TX VCO
Integrated loop filter
Integrated RF Frequency Synthesizer
Programmable fractional-N synthesizer
Integrated wide range RFVCO
Integrated loop filter
MediaTek Confidential
© 2009 MediaTek Inc.
Page 11 of 643
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT6253.PDF ] | |
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