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STI10N62K3 Datasheet PDF - STMicroelectronics

Part Number STI10N62K3
Description N-channel Power MOSFET
Manufacturers STMicroelectronics 
Logo STMicroelectronics Logo 

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STF10N62K3, STFI10N62K3,
STI10N62K3, STP10N62K3
N-channel 620 V, 0.68 typ., 8.4 A SuperMESH3™
Power MOSFET in TO-220FP, I²PAKFP, I²PAK, TO-220 packages
Datasheet production data
Features
Type
VDSS
RDS(on)
max
ID
Pw
STF10N62K3
STFI10N62K3
STI10N62K3
STP10N62K3
620 V
< 0.75
8.4 A(1)
8.4 A
30 W
125 W
1. Limited by package
100% avalanche tested
Extremely high dv/dt capability
Gate charge minimized
Very low intrinsic capacitances
Improved diode reverse recovery
characteristics
Zener-protected
Applications
Switching applications
Description
These SuperMESH3™ Power MOSFETs are the
result of improvements applied to
STMicroelectronics’ SuperMESH™ technology,
combined with a new optimized vertical structure.
These devices boast an extremely low on-
resistance, superior dynamic performance and
high avalanche capability, rendering them suitable
for the most demanding applications.
Table 1. Device summary
Order codes
Marking
STF10N62K3
STFI10N62K3
STI10N62K3
STP10N62K3
10N62K3
10N62K3
10N62K3
10N62K3
3
2
1
TO-220FP
1
23
I²PAKFP
TAB
TAB
123
I²PAK
3
2
1
TO-220
Figure 1. Internal schematic diagram
' 7$%
* 
6 
AM01476v1
Package
TO-220FP
I²PAKFP
I²PAK
TO-220
Packaging
Tube
September 2012
This is information on a product in full production.
Doc ID 15640 Rev 4
1/17
www.st.com
17

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STI10N62K3 equivalent
STF10N62K3, STFI10N62K3, STI10N62K3, STP10N62K3
Electrical characteristics
Table 6. Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
VDD = 310 V, ID = 4 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 17)
Min. Typ. Max. Unit
14.5 ns
15
-
41
ns
-
ns
31 ns
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
ISD
ISDM (1)
VSD (2)
Source-drain current
Source-drain current (pulsed)
Forward on voltage
ISD = 8 A, VGS = 0
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 8 A, di/dt = 100A/µs
VDD = 60 V (see Figure 22)
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 8 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
(see Figure 22)
1. Pulse width limited by safe operating area
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
Min. Typ. Max. Unit
8.4 A
-
33.6 A
- 1.5 V
320
-2
13
ns
µC
A
410
- 2.9
14
ns
µC
A
Table 8. Gate-source Zener diode
Symbol
Parameter
Test conditions
V(BR)GSO Gate-source breakdown
voltage (ID = 0)
Igs= ± 1 mA
Min. Typ. Max. Unit
30 - V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
Doc ID 15640 Rev 4
5/17


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