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What is EPM3256A?

This electronic component, produced by the manufacturer "Altera", performs the same function as "Programmable Logic Device Family".


EPM3256A Datasheet PDF - Altera

Part Number EPM3256A
Description Programmable Logic Device Family
Manufacturers Altera 
Logo Altera Logo 


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June 2003, ver. 3.4
®
MAX 3000A
Programmable Logic
Device Family
Data Sheet
Features...
High–performance, low–cost CMOS EEPROM–based programmable
logic devices (PLDs) built on a MAX® architecture (see Table 1)
3.3-V in-system programmability (ISP) through the built–in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
Built–in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
High–density PLDs ranging from 600 to 10,000 usable gates
4.5–ns pin–to–pin logic delays with counter frequencies of up to
227.3 MHz
MultiVoltTM I/O interface enabling the device core to run at 3.3 V,
while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic
levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier
(PLCC), and FineLine BGATM packages
Hot–socketing support
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
Industrial temperature range
Table 1. MAX 3000A Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
tPD (ns)
tSU (ns)
tCO1 (ns)
fCNT (MHz)
EPM3032A
600
32
2
34
4.5
2.9
3.0
227.3
EPM3064A
1,250
64
4
66
4.5
2.8
3.1
222.2
Altera Corporation
DS-MAX3000A-3.4
EPM3128A
2,500
128
8
98
5.0
3.3
3.4
192.3
EPM3256A
5,000
256
16
161
7.5
5.2
4.8
126.6
EPM3512A
10,000
512
32
208
7.5
5.6
4.7
116.3
1

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EPM3256A equivalent
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 1. MAX 3000A Device Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
INPUT/GCLRn
6 or 10 Output Enables (1)
2 to 16 I/O
LAB A
I/O
Control
Block
2 to
16
Macrocells
1 to 16
36
16
6 or 10 Output Enables (1)
LAB B
36 Macrocells
17 to 32
16
2 to
16 I/O
Control
Block
2 to 16 I/O
2 to 16 I/O
6 or 10
2 to 16
I/O
Control
Block
LAB C
2 to
16 Macrocells
33 to 48
PIA
36
16
2 to 16
6 or 10
LAB D
36 Macrocells
49 to 64
16
2 to
16 I/O
Control
Block
2 to 16 I/O
6 or 10
2 to 16
2 to 16
6 or 10
Note:
(1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have
10 output enables.
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of
high–performance LABs. LABs consist of 16–macrocell arrays, as shown
in Figure 1. Multiple LABs are linked together via the PIA, a global bus
that is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Altera Corporation
5


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Part Details

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Part NumberDescriptionMFRS
EPM3256AThe function is Programmable Logic Device Family. AlteraAltera

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