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PDF ATtiny15 Data sheet ( Hoja de datos )
| Número de pieza | ATtiny15 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• RISC Architecture
– 90 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Nonvolatile Program and Data Memories
– 1K Bytes of In-System Programmable Program Memory Flash
Endurance: 1,000 Write/Erase Cycles
– 64 bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– Two 8-bit Timers/Separate Prescalers
One High-speed (100 kHz) PWM Output
– 4-channel 10-bit ADC
One Differential Voltage Input with Optional Gain of 20X
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
• Special Microcontroller Features
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low-power Idle, Noise Reduction and Power Down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal 1.6 MHz Tuneable Oscillator
– Internal 25.6 MHz Clock Generator for Timer/Counter 1
• I/O and Packages
– 8-pin PDIP/SOIC: 6 Programmable I/O Lines
• Operating Voltages
– 2.7V - 5.5V (ATtiny15L)
– 4.0V - 5.5V (ATtiny15)
• Commercial and Industrial Temperature Ranges
8-bit
Microcontroller
with 1K Bytes
Flash
ATtiny15
Advance
Information
Description
The ATtiny15 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny15
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed
(continued)
Pin Configurations
PDIP/SOIC
(RESET/ADC0) PB5
(ADC3) PB4
(ADC2) PB3
GND
1
2
3
4
8 VCC
7 PB2 (SCK/ADC1/T0/INT0)
6 PB1 (MISO/AIN1/OCP)
5 PB0 (MOSI/AIN0/AREF)
Rev. 1187A–08/99
1
1 page  
ATtiny15
Table 3. Reset Delay Selections
CKSEL [1:0]
00
Start-up Time, tTOUT at VCC = 2.7V
128 µs + 18CK
01 16 ms + 18 CK
10 256 ms + 18 CK
11 256 ms + 1K CK
Start-up Time, tTOUT at VCC = 5.0V
32 µs + 18 CK
4 ms + 18 CK
64 ms + 18 CK
64 ms + 1K CK
Recommended Usage
BOD enabled
BOD disabled, quickly rising power
BOD disabled, slowly rising power
BOD disabled, slowly rising power
Brown-out Detection
ATtiny15 has an on-chip brown-out detection (BOD) circuit for monitoring the VCC level during the operation. The BOD cir-
cuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and VCC decreases
below the trigger level, the brown-out reset is immediately activated. When VCC increases above the trigger level, the
brown-out reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal,
in Table 3. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed),
or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis of 50 mV to ensure spike free brown-out detection.
The BOD circuit will only detect a drop in Vcc if the voltage stays below the trigger level for longer than 3 µs for trigger level
4.0V, 7 µs for trigger level 2.7V (typical values).
Figure 2. MCU Start-Up, RESET Controlled Externally
VCC
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL
RESET
Pin Change Interrupt
The pin change interrupt is triggered by any change on any input or I/O pin. Change on pins will cause an interrupt if the pin
is configured as input or I/O, as described in the section “Pin Descriptions”. Observe that, if enabled, the interrupt will trig-
ger even if the changing pin is configured as an output. This feature provides a way of generating a software interrupt. Also
observe that the pin change interrupt will trigger even if the pin activity triggers another interrupt, for example the external
interrupt. This implies that one external event might cause several interrupts.
Sleep Modes
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an
enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, The CPU is then halted for 4 cycles, it exe-
cutes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file
and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset
vector.
5
5 Page 
Prescaling
Figure 4. ADC Prescaler
ATtiny15
ADEN
CK
Reset
7-BIT ADC PRESCALER
ADPS0
ADPS1
ADPS2
ADC CLOCK SOURCE
The ADC contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADC accepts
input clock frequencies in the range 50 - 200 kHz. Applying a higher input frequency will result in a poorer accuracy, typi-
cally 8 bits at 1 MHz.
The ADPS0 - ADPS2 bits in ADCSR are used to generate a proper ADC clock input frequency from any XTAL frequency
above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR.
The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the
ADC clock cycle. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of the conversion. The result
is ready and written to the ADC Result Register after 13 cycles. In single conversion mode, the ADC needs one more clock
cycle before a new conversion can be started, see Figure 6. If ADSC is set high in this period, the ADC will start the new
conversion immediately. In Free Run Mode, a new conversion will be started immediately after the result is written to the
ADC Result Register. Using Free Run Mode and an ADC clock frequency of 200 kHz gives the lowest conversion time,
65 µs, equivalent to 15.4 kSPS. For a summary of conversion times, see Table 9.
Figure 5. ADC Timing Diagram, First Conversion (Single Conversion Mode)
;;;;Cycle number
;;;;ADC clock
;;;;ADEN
;;;;ADSC
;;;;Hold strobe
;;;;ADIF
;;ADCH
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;ADCL
12
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1
2
MSB of result
LSB of result
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;Second
Dummy Conversion
Actual Conversion
Conversion
11
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| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ATtiny15.PDF ] | |
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