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PDF AK5720 Data sheet ( Hoja de datos )
| Número de pieza | AK5720 | |
| Descripción | 96kHz 24-Bit ADC | |
| Fabricantes | AKM | |
| Logotipo |  |
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[AK5720]
AK5720
96kHz 24-Bit ADC
1. General Description
The AK5720 is a low voltage 24-bit A/D converter for digital audio systems. The AK5720 includes an
Input Gain Amplifier, making it suitable for microphone applications. The analog signal input of the
AK5720 is single-ended, eliminating the need for external filters. The AK5720 is housed in a
space-saving 16-pin TSSOP package.
2. Features
1. Resolution: 24bits
2. Recording Functions
Gain Amplifier (0dB / +15dB)
Digital HPF for DC-offset cancellation (fc=1.0Hz@fs=48kHz)
3. ADC Characteristics
Single-ended Input
Input Level: 1.8Vpp@VA=3.0V (= 0.6 × VA), 3.0Vpp@VA=5.0V (=0.6 × VA)
S/(N+D): 94dB
DR, S/N: 102dB
4. Master Clock: 256fs/384fs/512fs/768fs
5. Sampling Frequency: 8kHz 96kHz
6. Audio Data Format: MSB First, 2’s compliment
24-bit MSB justified, I2S and TDM
7. Power Supply
VA, VD: 2.7 5.5V (typ. 3V, 5V)
8. Power Supply Current: 6.1mA(VA-VD=5.0V,fs=48kHz)
9. Operating Temperature: Ta = -40 105C
10. Package: 16-pin TSSOP
GSEL
DIF/TDMI
LIN
RIN
VCOM
VA
REGO
VSS
Regulator
ADC
HPF
IIIS/TDM
Out
LRCK
BICK
SDTO
Clock Divider
FSEL
CKS
MCLK
VD
PDN
MS1641-E-02
-1-
2014/12
1 page  
5. Absolute Maximum Ratings
(VSS=0V; Note 1)
Parameter
Symbol
min
Power Supplies: Analog
VA 0.3
Digital
VD 0.3
Input Current, Any Pin Except Supplies
IIN -
Analog Input Voltage (LIN, RIN pins)
VINA
0.3
Digital Input Voltage
VIND
0.3
Ambient Temperature
Ta 40
Storage Temperature
Tstg 65
Note 1. All voltages with respect to ground.
[AK5720]
max
6.0
6.0
10
VA+0.3
VD+0.3
105
150
Unit
V
V
mA
V
V
C
C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal
operation is not guaranteed at these extremes. The AK5720 will be damaged if a voltage higher
than 2.5V is input to the REGO pin.
6. Recommended Operating Conditions
(VSS=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies Analog (VA pin)
VA 2.7
3 or 5
Digital (VD pin)
VD 2.7
3 or 5
Note 1. All voltages with respect to ground.
max Unit
5.5 V
VA V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1641-E-02
-5-
2014/12
5 Page 
[AK5720]
Parameter
Symbol min
typ max Unit
Audio Interface Timing (Slave mode)
Normal mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “”
(Note 8)
BICK “” to LRCK Edge
(Note 8)
LRCK to SDTO (MSB) (Except I2S
mode)
BICK “” to SDTO
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
160
65
65
30
30
ns
ns
ns
ns
ns
35 ns
35 ns
TDM256 mode
BICK Period
tBCK
40
ns
BICK Pulse Width Low
tBCKL
16
ns
Pulse Width High
LRCK Edge to BICK “”
BICK “” to LRCK Edge
SDTO Setup time BICK “”
SDTO Hold BICK “”
(Note 8)
(Note 8)
tBCKH
tLRB
tBLR
tBSS
tBSH
16
10
10
7
6
ns
ns
ns
ns
ns
TDMI Hold Time
tSDH
4
ns
TDMI Setup Time
tSDS
5
ns
Audio Interface Timing (Master mode)
Normal mode
BICK Frequency
fBCK 64fs Hz
BICK Duty
BICK “” to LRCK
BICK “” to SDTO
dBCK
50
%
tMBLR
20
20 ns
tBSD
40
40 ns
TDM256 mode
BICK Frequency
fBCK
256fs
Hz
BICK Duty
(Note 9) dBCK
50
%
BICK “” to LRCK
tMBLR
10
10 ns
SDTO Setup time BICK “”
tBSS
7
ns
SDTO Hold BICK “”
tBSH
6
ns
TDMI Hold Time
tSDH
4
ns
TDMI Setup Time
tSDS
5
ns
Power-Down & Reset Timing
PDN Pulse Width
PDN Reject Pulse Width
PDN “” to SDTO valid
(Note 10)
(Note 10)
(Note 11)
tPD
tRPD
tPDV
150
4129
30
ns
ns
1/fs
Note 8. BICK rising edge must not occur at the same time as LRCK edge.
Note 9. In the case of MCLK duty cycle is 50%.
Note 10. The AK5720 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L”
for more han 150ns for a certain reset. The AK5720 is not reset by the “L” pulse less than 30ns.
Note 11. This is the count of LRCK “↑” from the PDN pin = “H”.
MS1641-E-02
- 11 -
2014/12
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AK5720.PDF ] | |
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