LM9820 Datasheet PDF - National Semiconductor
Part Number | LM9820 | |
Description | 10/12-Bit Image Sensor Processor Analog Front End | |
Manufacturers | National Semiconductor | |
Logo | ||
There is a preview and LM9820 download ( pdf file ) link at the bottom of this page. Total 21 Pages |
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LM9810/LM9820
10/12-Bit Image Sensor Processor Analog Front End
General Description
The LM9810 and LM9820 are high performance Analog
Front Ends (AFEs) for image sensor processing systems.
The LM9810/20 performs all the analog and mixed signal
functions (correlated double sampling, color specific gain
and offset correction, and analog to digital conversion) nec-
essary to digitize the output of a wide variety of CIS and CCD
sensors. The LM9810 has a 10-bit 6 MHz ADC, and the
LM9820 has a 12-bit 6 MHz ADC. The LM9810 and LM9820
are pin-for-pin and functionally compatible.
Key Specifications
n Output Data Resolution
n Pixel Conversion Rate
n Supply Voltage
n Power Dissipation
10/12 Bits
6 MHz
5V ±5%
300 mW
Features
n 6 million pixels/s conversion rate
n Digitally programmed gain and offset for red, green and
blue pixels
n Correlated Double Sampling for lowest noise
n TTL/CMOS input/output compatible
Applications
n Color Flatbed Document Scanners
n Color Sheetfed Scanners
n Multifunction Imaging Products
n Digital Copiers
n General Purpose Linear CCD Imaging
Connection Diagram
Ordering Information
Commercial (0˚C ≤ TA ≤ +70˚C)
LM9810CCWM
LM9810CCWMX
LM9820CCWM
LM9820CCWMX
DS100943-69
Package
20-Pin Wide SOIC
20-Pin Wide SOIC, Tape and Reel
20-Pin Wide SOIC
20-Pin Wide SOIC, Tape and Reel
© 2000 National Semiconductor Corporation DS100943
www.national.com
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LM9820 Electrical Characteristics (Continued)
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, RS = 25Ω. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. All LSB limits are in units of the LM9810’s 12-bit ADC.
(Notes 7, 8, 12)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9) (Note 10) (Limits)
SYSTEM CHARACTERISTICS (SEE SECTION 1.7.1, INTERNAL OFFSETS)
VOS1
Pre-Boost Analog Channel Offset Error,
CIS Mode
18
-22.2
LSB (min)
+57 LSB (max)
VOS2
Pre-PGA Analog Channel Offset Error
-40
-94.3
LSB (min)
+16.4
LSB (max)
VOS3
Post-PGA Analog Channel Offset Error
-44
-121
LSB (min)
+28 LSB (max)
DC and Logic Electrical Characteristics
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, Rs = 25Ω. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9) (Note 10) (Limits)
D0–D2, MCLK, NewLine, SampCLK DIGITAL INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VD = 5.25V
VIN(0)
Logical “0” Input Voltage
VD = 4.75V
IIN Input Leakage Current
VIN = VD
VIN = DGND
CIN Input Capacitance
D0–D5, DIGITAL OUTPUT CHARACTERISTICS
0.1
−0.1
5
2.0 V (max)
0.8 V (min)
µA (max)
µA (max)
pF
VOUT(1) Logical “1” Output Voltage
VOUT(0)
IOUT
Logical “0” Output Voltage
TRI-STATE® Output Current
(D0–D5 only)
POWER SUPPLY CHARACTERISTICS
VD = 4.75V, IOUT = −360 µA
VD = 4.75V, IOUT = −10 µA
VD = 5.25V, IOUT = 1.6 mA
VOUT = DGND
VOUT = VD
0.1
−0.1
2.4 V (min)
4.4 V (min)
0.4 V (max)
µA
µA
IA Analog Supply Current
Operating
Standby with Input Clocks Stopped
45 57 mA (max)
0.8 0.9 mA (max)
Standby with Input Clocks Running
3.0
mA
ID Digital Supply Current (Note 15) Operating
220 320 µA (max)
Standby with Input Clocks Stopped
110 200 µA (max)
Standby with Input Clocks Running
220
µA
AC Electrical Characteristics
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, tMCLK = 1/fMCLK,
tr = tf = 5 ns, Rs = 25Ω. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
fMCLK
Maximum MCLK Frequency
MCLK Duty Cycle
24 MHz (min)
40
(min)
60
(max)
tMCLK
tSCNL
MCLK Period
SampCLK Falling Edge before NewLine
Falling Edge
41 ns (min)
3 tMCLK (min)
tSampCLK
tSampLo
SampCLK Period
Low Time for SampCLK
4 tMCLK (min)
50 ns (min)
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Information | Total 21 Pages | |
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