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What is 73M1903?

This electronic component, produced by the manufacturer "Teridian Semiconductor", performs the same function as "Modem Analog Front End".


73M1903 Datasheet PDF - Teridian Semiconductor

Part Number 73M1903
Description Modem Analog Front End
Manufacturers Teridian Semiconductor 
Logo Teridian Semiconductor Logo 


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Simplifying System IntegrationTM
DESCRIPTION
The Teridian 73M1903 Analog Front End (AFE) IC
includes fully differential hybrid driver outputs, which
connect to the telephone line interface through a
transformer-based DAA. The receive pins are also
fully differential for maximum flexibility and
performance. This arrangement allows for the
design of a high performance hybrid circuit to
improve signal to noise performance under low
receive level conditions, and compatibility with any
standard transformer intended for PSTN
communications applications.
The device incorporates a programmable sample
rate circuit to support soft modem and DSP based
implementations of all speeds up to V.92 (56 kbps).
The sampling rates supported are from 7.2 kHz to
14.4 kHz by programming pre-scaler NCO and PLL
NCO.
The 73M1903 device incorporates a digital host
interface that is compatible with the serial ports
found on most commercially available DSPs and
processors and exchanges both payload and control
information with the host.
Cost-saving features of the device include an input
reference frequency circuit, which accepts a range
of crystals from 9-27 MHz. It also accepts external
reference clock values between 9-40 MHz
generated by the host processor. In most
applications, this eliminates the need for a dedicated
crystal oscillator and reduces the bill of material
(BOM).
The 73M1903 also supports two analog loop back
and one digital loop back test modes.
(HYBRID)
VBG
TXAP
TXAN
Transmit
Drivers/
Filters
Analog
Sigma
Delta
Ref.
SCLK
RXAP
RXAN
Receive
Mux/
Filters
Control Serial
DAC Registers Port
SDIN
SDOUT
FSB
GPIO
HOOK
DAA
Controls Clocks
Control
Logic
Crystal
73M1903
Modem Analog Front End
DATA SHEET
March 2010
FEATURES
Up to 56 kbps (V.92) performance
Programmable sample rates (7.2 - 14.4 kHz)
Reference clock range of 9-40 MHz
Crystal frequency range of 9-27 MHz
Host synchronous serial interface operation
Pin compatible with 73M2901CL/CE
modems
Low power modes
On board line interface drivers
Fully differential receiver and transmitter
Drivers for transformer interface
3.0 V – 3.6 V operation
5 V tolerant I/O
Industrial temperature range (-40 to +85 °C)
JATE compliant transmit spectrum
Package options:
32-pin QFN
20-pin TSSOP
RoHS compliant (6/6) lead-free packages
APPLICATIONS
Set Top Boxes
Personal Video Recorders (PVR)
Multifunction Peripherals (MFP)
Fax Machines
Internet Appliances
Game Consoles
Point of Sale Terminals
Automatic Teller Machines
Speaker Phones
RF Modems
Rev. 2.1
© 2010 Teridian Semiconductor Corporation
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73M1903 equivalent
DS_1903_032
73M1903 Data Sheet
1.1 Serial Interface
The serial data port is a bi-directional port that is supported by many DSPs. Although the 73M1903 is a
peripheral to the DSP (host controller), the 73M1903 is the master of the serial port. It generates a serial
bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that is
programmed by the user. The serial bit clock is derived by dividing the system clock by 18. The sclk rate,
Fsclk, is related to the frame synchronization rate, Fs, by the relationship Fsclk = 256 x Fs or Fs = Fsclk /
256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is also the rate at which
both the transmit and receive data bytes are sent (received) to (by) the Host. Throughout this document
two pairs of sample rates, Fs, and crystal frequency, Fxtal, will be often cited to facilitate discussions.
They are:
1. Fxtal1 = 27 MHz, Fs1 = 7.2 kHz
2. Fxtal2 = 18.432 MHz, Fs2 = 8 kHz.
3. Fxtal3 = 24.576 MHz, Fs3 = 9.6 kHz – chip default.
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be Sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal1 = 27.000 MHz, then sclk=1.500 MHz and Fs=sclk/256 = 5.859375 kHz.
2. If Fxtal2 = 18.432 MHz, then sclk=1.024 MHz and Fs=sclk/256 = 4.00 kHz.
3. If Fxtal3 = 24.576 MHz, then sclk=1.3653 MHz and Fs=sclk/256 = 5.33 kHz.
When 73M1903 is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1. If Fs1 = 7.2 kHz, Fsys = 4608 * Fs = 33.1776 MHz and sclk = Fsys / 18 = 1.8432 MHz.
2. If Fs2 = 8.0 kHz, Fsys = 4608 * Fs = 36.8640 MHz and sclk = Fsys / 18 = 2.048 MHz.
3. If Fs3 = 9.6 kHz, Fsys = 4608 * Fs = 44.2368 MHz and sclk = Fsys / 18 = 2.4576 MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting a bit in a
designated serial port register – location bit 7, 0Eh. The transition is forced on or after the second Frame
Synch period following the write to a designated PLL programming register (0Dh).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),
ENFE=0.
During the normal operation, a data FS is generated by the 73M1903 at the rate of Fs. For every data FS
there are 16 bits transmitted and 16 bits received. The frame synchronization (FS) signal is pin
programmable for type. FS can either be early or late determined by the state of the TYPE input pin.
When the TYPE pin is left open, an early FS is generated in the bit clock prior to the first data bit
transmitted or received. When held low, a late FS operates as a chip select; the FS signal is active for all
bits that are transmitted or received. The TYPE input pin is sampled when the reset pin is active (low)
and ignored at all other times. The final state of the TYPE pin as the reset pin is de-asserted determines
the frame synchronization mode used.
Rev. 2.1
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