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PDF FE1.1S Data sheet ( Hoja de datos )
| Número de pieza | FE1.1S | |
| Descripción | USB 2.0 HIGH SPEED 4-PORT HUB CONTROLLER | |
| Fabricantes | JFD | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de FE1.1S (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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USB 2.0 4-Port Hub
Data Sheet Rev. 1.0
www.jfd-ic.com
FE1.1S
USB 2.0 HIGH SPEED 4-PORT HUB CONTROLLER
_______________________Data Sheet_______________________
INTRODUCTION
The FE1.1s is a highly integrated, high quality,
high performance, low power consumption, yet
low cost solution for USB 2.0 High Speed 4-Port
Hub.
It adopts Single Transaction Translator (STT)
architecture to be more cost effective. Six,
instead of two, non-periodic transaction buffers
are used to minimize potential traffic jamming.
The whole design is based on state-machine-
control to reduce the response delay time; no
micro controller is used in this chip.
To guarantee high quality, the whole chip is
covered by Test Scan Chain – even on the high
speed (480MHz) modules, so that all the logic
components could be fully tested before shipping.
Special Build-In-Self-Test mode is designed to
exercise all high, full, and low speed Analog
Front End (AFE) components on the packaging
and testing stages as well.
Low power consumption is achieved by using
0.18μm technology and comprehensive
power/clock control mechanism. Most part of the
chip will not be clocked unless needed.
FEATURES
Fully compliant with Universal Serial Bus
Specification Revision 2.0 (USB 2.0);
□ Upstream facing port supports High-
Speed (480MHz) and Full-Speed
(12MHz) modes;
□ 4 downstream facing ports support
High-Speed (480MHz), Full-Speed
(12MHz), and Low-Speed (1.5MHz)
modes;
Integrated USB 2.0 Transceivers;
Integrated upstream 1.5KΩ pull-up,
downstream 15KΩ pull-down, and serial
resisters;
Integrated 5V to 3.3V and 1.8V regulator.
Integrated Power-On-Reset circuit;
Integrated 12MHz Oscillator with feedback
resister, and crystal load capacitance;
Integrated 12MHz-to-480MHz Phase Lock
Loop (PLL);
Single Transaction Translator (STT) –
□ One TT for all downstream ports;
□ The TT could handle 64 periodic Start-
Split transactions, 32 periodic
Complete-Split transactions, and 6
none-periodic transactions;
Automatic self-power status monitoring;
□ Automatic re-enumeration when Self-
NOV. 29, 2008
Subject to Change Without Notice
1
1 page  
USB 2.0 4-Port Hub
Data Sheet Rev. 1.0
PIN DESCRIPTION TABLE
Pin Name LQFP SSOP Type
Pin No. Pin No.
Function
Note
VSS
XOUT
XIN
DM4
DP4
DM3
DP3
DM2
DP2
DM1
DP1
VD18_O
10
11
12
14
15
17
18
20
21
23
24
26
VD33
REXT
27
28
DMU
DPU
XRSTJ
30
31
34
VBUSM
BUSJ
35
36
VDD5
VD33_O
38
39
TEST
40
DRV
42
1
2
3
4
5
6
7
8
9
10
11
12
13
14
25
16
17
18
19
20
21
―—
22
P Ground.
OSC 12 MHz Crystal Oscillator output
OSC 12 MHz Crystal Oscillator input.
UT The D- pin of the 4th Downstream Facing Port.
UT The D+ pin of the 4th Downstream Facing Port.
UT The D- pin of the 3rd Downstream Facing Port.
UT The D+ pin of the 3rd Downstream Facing Port.
UT The D- pin of the 2nd Downstream Facing Port.
UT The D+ pin of the 2nd Downstream Facing Port.
UT The D- pin of the 1st Downstream Facing Port.
UT The D+ pin of the 1st Downstream Facing Port.
P 1.8V power output from 3.3V→1.8V integrated regulator – a
10μF decoupling capacitor is required.
P 3.3V power input for 3.3V→1.8V integrated regulator.
A 2.7KΩ (± 1%) resister should be connected to VSS to
provide internal bias reference.
UT The D- pin of the Upstream Facing Port.
UT The D+ pin of the Upstream Facing Port.
I External Reset, active low, is an optional source of chip reset
signal, beside the build-in Power-On-Reset. The minimum low
pulse width is 10 μs.
I The VBUS Monitor of upstream facing port.
I Bus power indicator:
0 – Bus Powered; 1 – Self Powered.
P 5V power input for integrated 5V→3.3V regulator.
P 3.3V power output from 5V→3.3V integrated regulator – a
10μF decoupling capacitor is required.
I Test Mode Enable – should be tied to ground for normal
operation.
I/O LED Drive Control
1
NOV. 29, 2008
Subject to Change Without Notice
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet FE1.1S.PDF ] | |
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