|
|
PDF NCV7710 Data sheet ( Hoja de datos )
| Número de pieza | NCV7710 | |
| Descripción | Door-Module Driver-IC | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NCV7710 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
NCV7710
Door-Module Driver-IC
(Lock Driver-IC)
The NCV7710 is a powerful Driver−IC for automotive body control
systems. The IC is designed to control lock motor in the door of a
vehicle. With the monolithic full−bridge driver stage, the IC is able to
control lock motor. The NCV7710 is controlled thru a 24 bit SPI
interface with in−frame response.
Features
• Operating Range from 5.5 V to 28 V
• Two High−Side and Two Low−Side Drivers Connected as
Half−bridges
♦ 2 Half−bridges Iload = 6 A; Rdson = 150 mW @ 25°C
• Programmable Soft−Start Function to Drive Loads with Higher
Inrush Currents as Current Limitation Value
• Support of PWM Control Frequency Outside the Audible Noise
• Support of Active Freewheeling to Reduce Power Dissipation
• Multiplex Current Sense Analog Output for Advanced Load
Monitoring
• Very Low Current Consumption in Standby Mode
• Charge Pump Output to Control an External Reverse Polarity
Protection MOSFET
• 24−Bit SPI Interface for Output Control and Diagnostic
• Protection Against Short Circuit, Overvoltage and Over−temperature
• Downwards Pin−to−pin and SPI Registers Compatible with
NCV7707
• SSOP36−EP Power Package
• AEC−Q100 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• De−centralized Door Electronic Systems
• Rear Door Electronic Unit
• Body Control Units (BCUs)
• Several H−bridge Applications
www.onsemi.com
SSOP36−EP
DQ SUFFIX
CASE 940AB
MARKING DIAGRAM
NCV7710
AWLYYWWG
NCV7710 = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 0
1
Publication Order Number:
NCV7710/D
1 page  
NCV7710
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Min Max Unit
Power supply voltage
Vs − Continuous supply voltage
− Transient supply voltage (t < 500 ms, “clamped load dump”)
−0.3 28 V
−0.3 40
Vcc Logic supply
−0.3 5.5 V
Vdig
DC voltage at all logic pins (SO, SI, SCLK, CSB, PWM1)
−0.3
Vcc + 0.3
V
Visout/pwm2 Current monitor output / PWM2 logic input
−0.3
Vcc + 0.3
V
Vchp
Charge pump output (the most stringent value is applied)
−25
Vs − 25
40
Vs + 15
V
Voutx
Static output voltage (OUT1/2)
−0.3
Vs + 0.3
V
Iout1/2
OUT1/2 Output current
−10 10 A
ESD_HBM
ESD Voltage, HBM (Human Body Model); (100 pF, 1500 W) (Note 1)
− All pins
− Output pins OUT1/2 to GND (all unzapped pins grounded)
−2
−4
2 kV
4
ESD_CDM
ESD according to CDM (Charge Device Model) (Note 1)
− All pins
− Corner pins
−500
−750
500 V
750
TJ Operating junction temperature range
Tstg Storage temperature range
−40 150 °C
−55 150 °C
MSL
Moisture sensitivity level (Note 2)
MSL3
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charge Device Model tested per EIA/JES D22/C101, Field Induced Charge Model
2. For soldering information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Symbol
Rating
Value
Unit
RθJA
Thermal Characteristics, SSOP36−EP, 1−layer PCB
Thermal Resistance, Junction−to−Air (Note 3)
49.4 °C/W
RθJA
Thermal Characteristics, SSOP36−EP, 4−layer PCB
Thermal Resistance, Junction−to−Air (Note 4)
24 °C/W
3. Values based on PCB of 76.2 x 114.3 mm, 72 mm copper thickness, 20 % copper area coverage and FR4 PCB substrate.
4. Values based on PCB of 76.2 x 114.3 mm, 72 / 36 mm copper thickness (signal layers / internal planes), 20 / 90 % copper area coverage
(signal layers / internal planes) and FR4 PCB substrate.
www.onsemi.com
5
5 Page 
NCV7710
DETAILED OPERATING AND PIN DESCRIPTION
General
The NCV7710 provides two half−bridge drivers. Strict
adherence to integrated circuit die temperature is necessary,
with a static maximum die temperature of 150°C. Output
drive control and fault reporting are handled via the SPI
(Serial Peripheral Interface) port. A SPI−controlled mode
control provides a low quiescent sleep current mode when
the device is not being utilized. A pull down is provided on
the SI and SCLK inputs to ensure they default to a low state
in the event of a severed input signal. A pull−up is provided
on the CSB input disabling SPI communication in the event
of an open CSB input.
Supply Concept
Power Supply Scheme − VS and VCC
The Vs power supply voltage is used to supply the half
bridges and the high−side drivers. An all−internal
chargepump is implemented to provide the gate−drive
voltage for the n−channel type high−side transistors. The
VCC voltage is used to supply the logic section of the IC,
including the SPI interface.
Due to the independent logic supply voltage the control
and status information will not be lost in case of a loss of Vs
supply voltage. The device is designed to operate inside the
specified parametric limits if the VCC supply voltage is
within the specified voltage range (4.5 V to 5.25 V).
Between the operational level and the VCC undervoltage
threshold level (Vuv_VCC) it is guaranteed that the device
remains in a safe functional state without any inadvertent
change to logic information.
Device / Module Ground Concept
The heat slug is not hard−connected to internal GND rail.
It has to be connected externally.
Power Up/Down Control
In order to prevent uncontrolled operation of the device
during power/up down, an undervoltage lockout feature is
implemented. Both supply voltages (VCC and Vs) are
monitored for undervoltage conditions supporting a safe
power−up transition. When Vs drops below the
undervoltage threshold Vuv_vs(off) (Vs undervoltage
threshold) both output stages are switched to
high−impedance state and the global status bit UOV_OC is
set. This bit is a multi information bit in the Global Status
Byte which is set in case of overcurrent, Vs over− and
undervoltage. In case of undervoltage the status bit
STATUS_2.VSUV is set, too.
Bit CONTROL_3.OVUVR (Vs under−/overvoltage
recovery behavior) can be used to select the desired recovery
behavior after a Vs under−voltage event. In case of OVUVR
= 0, both output stages return to their programmed state as
soon as Vs recovers back to its normal operating range. If
OVUVR is set, the automatic recovery function is disabled
thus the output stages will remain in high−impedance
condition until the status bits have been cleared by the
microcontroller. To avoid high current oscillations in case of
output short to GND and low Vs voltage conditions, it is
recommended to disable the Vs−auto−recovery by setting
OVUVR = 1.
Chargepump
In Standby mode, the chargepump is disabled. After
enabling the device by setting bit CONTROL_0.MODE to
active (1), the internal oscillator is started and the voltage at
the CHP output pin begins to increase. The output drivers are
enabled after a delay of tsact once MODE was set to active.
Driver Outputs
Output PWM Control
For both−half bridge outputs the device features the
possibility to logically combine the SPI−setting with a PWM
signal that can be provided to the inputs PWM1 and
ISOUT/PWM2, respectively. Each of the outputs has a fixed
PWM signal assigned which is shown in Table 1. The PWM
modulation is enabled by the respective bits in the control
registers (CONTROL_2.OUTx_PWMx). In case of using
pin ISOUT/PWM2, the application design has to take care
of either disabling the current sense feature or to provide
sufficient overdrive capability to maintain proper logic input
levels for the PWM input. To improve power performances,
fast PWMing up to 30 kHz is foreseen.
By setting PWM_SWAP bit in the configurations register
CONFIG it is possible to map both outputs to PWM1.
This is useful if PWM control and current sensing is
required at OUT1 and OUT2.
Table 1. PWM CONTROL SCHEME
PWM Control Input
Output CONFIG.PWM_SWAP = 0 CONFIG.PWM_SWAP = 1
OUT1
PWM1
PWM1
OUT2
PWM2
PWM1
In case of using pin ISOUT/PWM2, the application
design can decide:
• To control all PWM via PWM1 by setting bit
CONFIG.PWM_SWAP to 1
• or to disable the current sense feature
• or to provide sufficient overdrive capability to maintain
proper logic input levels for the PWM input
Due to the used external network connected between
microcontroller and ISOUT/PWM2 pin, the digital input
signal cannot be guaranteed to be a clean digital high or low
level when the current output ISOUT is activated. During
Current sense the PWM2 digital input stays functional (the
input to the digital is not gated), but the internal pull down
on PWM2 is disabled when CS is activated.
www.onsemi.com
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet NCV7710.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NCV7710 | Door-Module Driver-IC | ON Semiconductor |
| NCV7718 | Hex Half-Bridge Driver | ON Semiconductor |
| NCV7718B | Hex Half-Bridge Driver | ON Semiconductor |
| NCV7719 | Octal Half-Bridge Driver |  ON Semiconducto |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |