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AFE1230 Datasheet PDF - Burr-Brown Corporation

Part Number AFE1230
Description G.SHDSL ANALOG FRONT-END
Manufacturers Burr-Brown Corporation 
Logo Burr-Brown Corporation Logo 
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AFE1230 datasheet, circuit
AFE1230
AFE1230
SBWS015A – AUGUST 2001
G.SHDSL ANALOG FRONT-END
FEATURES
q E1, T1, AND SUBRATE OPERATION
q COMPLIES WITH G.SHDSL AND HDSL2
q 16-BIT, DELTA-SIGMA CONVERTERS
q ON-CHIP DRIVER AND PGA
q PROGRAMMABLE tx AND rx FILTERS
q SERIAL DIGITAL INTERFACE
q 750mW POWER DISSIPATION AT E1
q +5V POWER (5V OR 3.3V DIGITAL)
q SSOP-28 PACKAGE
q –40°C TO +85°C TEMPERATURE RANGE
DESCRIPTION
Texas Instrument’s analog front-end chip, the AFE1230, is
designed to greatly reduce the size and cost of G.SHDSL
and HDSL2 application designs. It provides a transceiver as
the line interface between the Digital Signal Processor
(DSP) and the local loop. The AFE1230 is designed to
handle upstream and downstream data transmission over a
wide range of data rates from 64kbps to 2.5Mbps. Function-
ally, this unit consists of a transmitter and receiver section.
The transmitter section consists of a digital interpolation
filter, a 16-bit, delta-sigma Digital-to-Analog (D/A) con-
verter, a digitally programmable fifth-order or seventh-order
SC (Switched Capacitor) low-pass filter, and a differential
output line driver. The receiver section includes an input
Programmable Gain Amplifier (PGA), a 16-bit, delta-sigma
Analog-to-Digital (A/D) converter, and a programmable
decimation filter.
The AFE1230 receives a 16-bit data word plus an 8-bit control
byte via the serial interface to facilitate the D/A conversion
and control functions. The subsequent analog signal is sent to
the on-chip line driver that provides 14.5dBm power into a
135line for G.SHDSL operation. In addition, the on-chip
line driver can be used as an output buffer with an external line
driver, such as the OPA2677, to generate over 17dBm power
into a 135line for HDSL2 operation. With an appropriate
DSP, the transmitted Power Spectral Density (PSD) complies
with either the G.SHDSL standard or with the HDSL2 stan-
dard (via an OPA2677 used as an external driver).
In the receive path, the input amplifier sums the signals from
the line and hybrid path to perform first-order analog echo
cancellation. The resultant signal is then digitized by the rest
of the receive section into a 16-bit digital word that is sent to
the external DSP.
This IC operates on a single 5V supply, while the digital supply
can be from 3.3V to 5V. It is housed in a SSOP-28 package.
The typical power consumption is 750mW at E1 rates with
G.SHDSL (560mW for HDSL2 operation) and an operation
temperature range of –40°C to +85°C.
Digital
Interpolation
LPF
∆Σ 16-Bit
D/A Converter
Programmable
SC
LPF
Driver/
Buffer
txLINE
txLINE
MCLK
txBaud
txData
rxBaud
rxData
tx and rx
Digital
Interface
Registers
Programmable
Digital
LPF
∆Σ 16-Bit
A/D Converter
PGA
Input
Amplifier
hybINPUT
hybINPUT
rxINPUT
rxINPUT
AFE1230
Patents Pending
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2001, Texas Instruments Incorporated

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AFE1230 pdf, schematic
ABSOLUTE MAXIMUM RATINGS
Analog Input: Current ................................................ ±100mA, Momentary
Analog Input: Current .................................................. ±10mA, Continuous
Analog Input: Voltage ................................... AGND –0.3V to AVDD +0.3V
Analog Outputs Short-Circuit to Ground (+25°C) ..................... Continuous
AVDD to AGND ...................................................................... –0.3V to +6V
DVDD to DGND ...................................................................... –0.3V to +6V
Digital Input Voltage to DGND .................................. –0.3V to DVDD +0.3V
Digital Output Voltage to DGND ............................... –0.3V to DVDD +0.3V
AGND, DGND Differential Voltage ..................................................... 0.3V
Junction Temperature (Tj) ............................................................... 150°C
Storage Temperature Range .......................................... –40°C to +125°C
Lead Temperature Range (soldering, 3s) ...................................... +260°C
Power Dissipation ........................................................................ 1000mW
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
AFE1230E
AFE1230E/1K
PACKAGE
SSOP-28
"
PACKAGE
DRAWING
NUMBER
324
"
PACKAGE
DESIGNATOR
DBQ
"
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
"
PACKAGE
MARKING
AFE1230E
"
ORDERING
NUMBER(1)
AFE1230E
AFE1230E/1K
TRANSPORT
MEDIA
Rail
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “AFE1230E/1K” will get a single 1000-piece Tape and Reel. The AFE1230E/1K can only be ordered in 1000-unit increments.
PIN CONFIGURATION
Top View
SSOP
DVDD
GNDD
1
2
txBaud 3
txData 4
MCLK 5
rxBaud 6
rxData 7
DVDD
GNDD
8
9
GNDA 10
HybP 11
HybM 12
LineP 13
LineM 14
AFE1230
28 GNDA
27 GNDA
26 txOutP
25 AVDD
24 txOutM
23 GNDA
22 AVDD
21 AVDD
20 AVDD
19 VREFM
18 VCM
17 VREFP
16 GNDA
15 GNDA
PIN DESCRIPTIONS
PIN NAME
TYPE
1 DVDD
2 GNDD
3 txBaud
4 txData
5 MCLK
6 rxBaud
7 rxData
8 DVDD
9 GNDD
10 GNDA
11 HybP
12 HybM
13 LineP
14 LineM
15 GNDA
16 GNDA
17 VREFP
18 VCM
19 VREFM
20 AVDD
21 AVDD
22 AVDD
23 GNDA
24 txOutM
25 AVDD
26 txOutP
27 GNDA
28 GNDA
Power
Ground
Input
Input
Input
Input
Output
Power
Ground
Ground
Input
Input
Input
Input
Ground
Ground
Output
Output
Output
Power
Power
Power
Ground
Output
Power
Output
Ground
Ground
DESCRIPTION
Digital Supply
Digital Ground
Transmit Baud Clock
Digital Input of Transmit Section
Master Clock 48x Clock
Recieve Baud Clock
Digital Output of Recieve Section
Digital Supply
Digital Ground
Analog Ground
Positive Hybrid Input
Negative Hybrid Input
Positive Line Input
Negative Line Input
Analog Ground—Recieve
Analog Ground—Reference
Positive Reference Voltage, rx/tx
Common-Mode Voltage, rx/tx
Negative Reference Input, rx/tx
Analog Supply—Reference
Analog Supply—Recieve
Analog Supply—Transmit
Analog Ground/Driver
Line Driver Output Negative
Analog Supply/Driver
Line Driver Output Positive
Analog Ground/Driver
Analog Ground Transmit
2 AFE1230
SBWS015A

2 Page
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AFE1230 equivalent
0
50
100
150
200
250
300
103
102
101
100
FIGURE 2. Overall Transmit Filter. D/A Converter Frequency Response, Fifth-Order with 0.25x, 0.38x, and 0.5x.
0
50
100
150
200
250
300
350
103
102
101
100
FIGURE 3. Overall Transmit Filter. D/A Converter Frequency Response, Seventh-Order with 0.25x, 0.38x, and 0.5x.
Receive Filter
The receive filter consists of three independent sections used
for both the removal of quantization noise as well as the
reduction of data rate (otherwise known as downsampling).
The first section is comprised of a sinc5 filter with a
downsampling ratio of 12x. The resulting digital signal is then
passed to a droop compensation filter before being sent
through the final IIR filter section, while being downsampled
by two. Two filter cutoff configurations are available, as seen
in Table II. The corresponding cutoff frequencies relate to the
full-rate low-pass filter spectral template of the filter, as seen
from the inputs of Table II.
rx CUTOFF (txData Bit 24)
RATIO (Corner Frequency)
0 0.25 MCLK/24
1 0.5 MCLK/24
TABLE II. rx Filter Cutoff Frequency Setting.
Transmit Power
The on-chip differential line driver is designed to drive G.SHDSL
power levels directly, or it can be used as a low-power buffer for
driving a higher power external driver (for example the OPA2677)
for applications such as HDSL2. The AFE1230 driver will
generate an output swing of 6.2V peak-to-peak differential.
When used with a suitable transformer (see Figures 8 and 10),
the AFE1230 can generate up to 14.5dBm of power into a 135
line load. When used as a buffer with an OPA2677 driver,
17dBm of power can be generated. Relative transmit power can
be controlled digitally through control bits sent to the transmit
section by the serial interface. Relative transmit power reduction
can be set to 0, –6, –12, or –18dB, depending on the control bits
presented to the AFE1230, as shown in Table III.
TRANSMIT POWER
BACK OFF CODE
(txData Bits 25, 26)
TRANSMIT
POWER
REDUCTION
TRANSMIT POWER
G.SHDSL HDSL2
00 0dB 14.5dBm 17.0dBm
01
6dB
8.5dBm 11.0dBm
10
12dB
2.5dBm
5.0dBm
11
18dB
4.5dBm 1.0dBm
TABLE III. Transmit Power Backoff.
AFE1230
SBWS015A
5

5 Page
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AFE1230 diode, scr
MSB
16
8 16
8
Spare
rx Data Word 2
Spare
rx Data Word 1
TABLE VI. rx Data Structure.
BIT
47-32
31-24
23-8
7-0
DESCRIPTION
rx A/D Converter Word 1
Reserved
rx A/D Converter Word 2
Reserved
TABLE VII. rx Data Format.
BIT STATE
XXXX
Set All Bits Always to 0
XXXX
Set All Bits Always to 0
OUTPUT STATE
16-Bit Binary Two's Complement Word from rx A/D Converter (MSB First)
Reserved for Future Use
16-Bit Binary Two's Complement Word from rx A/D Converter (MSB First)
Reserved for Future Use
Digital Data Scale
The digital input and output data is coded in Binary Two’s
complement with 16 bits; the scale is shown in Table VIII.
ANALOG INPUT
Positive Full Scale
Mid Scale
Negative Full Scale
A/D CONVERTER DATA
MSB
LSB
0111111111111111
0000000000000000
1000000000000000
TABLE VIII. Digital Input/Output Data Scale.
Sampling Phase
The DSP will determine the sampling phase used for the
AFE1230. In the case of a phase jump (i.e.: when the rxBaud
or txBaud symbol clocks move one MCLK period forward
or backward, resulting in 49 or 47 MCLK cycles per rxBaud),
the receive data will be invalid for six symbol periods while
the data settles to the final value.
Loop Back
The AFE1230 includes digital and analog loop-back options,
as shown in Table IX.
Echo Cancellation in the AFE1230
The rxHYB input is designed to be subtracted from the
rxLINE input for first-order echo cancellation. To accom-
plish this, note that the rxLINE input is connected to the
same polarity signal at the transformer (+ to + and – to –),
while the rxHYB input is connected to opposite polarity
through the compromise hybrid (– to + and + to –).
LOOPBACK
OPERATION
Loopback = 00
Loopback = 01
Loopback = 10
Loopback = 11
Normal Operation
Digital Loopback: Data In is Shortened to Data Out.
Analog Loopback: The rxLINE inputs are shortened to VCM, while the transmit and rxHYB inputs are connected normally.
Analog Loopback: The rxHYB inputs are shortened to VCM, while the transmit and rxLINE inputs are connected normally.
TABLE IX. Loopback Table.
AFE1230
SBWS015A
9

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