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PDF CTS100ELT22DG Data sheet ( Hoja de datos )
| Número de pieza | CTS100ELT22DG | |
| Descripción | Dual CMOS/TTL to Differential PECL Translator | |
| Fabricantes | CTS | |
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CTS100ELT22
Dual CMOS/TTL to Differential PECL Translator
MSOP8, SOIC8
FEATURES
0.5ns Typical Propogation Delay
<100ps Typical Output to Output Skew
Flow Through Pinouts
Differential PECL Output
RoHS Compliant Pb Free Packages
BLOCK DIAGRAM
DESCRIPTION
The CTS100ELT22 is a dual CMOS/TTL to differential PECL translator. Because PECL (Positive ECL)
levels are used, only VCC and ground are required. The small outline packaging and the low skew, dual
gate design of the CTS100ELT22 makes it ideal for applications that require the translation of a clock and
a data signal.
The CTS100ELT22 is a direct replacement for the ON Semi MC100ELT22, MC100LVELT22 and Micrel
SY89322V.
ENGINEERING NOTES
When the D input is left floating, the Q output is forced HIGH, and the Q output is forced LOW.
CTS100ELT22 Large Signal Bandwidth
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
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CTS100ELT22
Dual CMOS/TTL to Differential PECL Translator
MSOP8, SOIC8
PACKAGE DIMENSIONS
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
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RevB0215
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CTS100ELT22DG.PDF ] | |
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