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ICE3BR1065J Datasheet PDF - Infineon Technologies

Part Number ICE3BR1065J
Description Off-Line SMPS Current Mode Controller
Manufacturers Infineon Technologies 
Logo Infineon Technologies Logo 
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ICE3BR1065J datasheet, circuit
Version 2.1, 19 Nov 2012
CoolSET®-F3R
ICE3BR1065J
Off-Line SMPS Current Mode
Controller with integrated 650V
CoolMOS®and Startup cell
(frequency jitter Mode) in DIP-8
Power Management & Supply
Never stop thinking.

1 page
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ICE3BR1065J pdf, schematic
CoolSET®-F3R
ICE3BR1065J
Revision History:
2012-11-19
Previous Version:
2.0
Page
Subjects (major changes since last revision)
27 revised outline dimension for PG-DIP-8 package
Datasheet Version 2.1
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://
www.infineon.com
CoolMOS®, CoolSET® are trademarks of Infineon Technologies AG.
Edition 2012-11-19
Published by
Infineon Technologies AG,
81726 Munich, Germany,
© 2012 Infineon Technologies AG.
All Rights Reserved.
Legal disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

2 Page
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ICE3BR1065J equivalent
CoolSET®-F3R
ICE3BR1065J
6 Input Power Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .29
Version 2.1
5 19 Nov 2012

5 Page
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ICE3BR1065J diode, scr
CoolSET®-F3R
ICE3BR1065J
Functional Description
The Undervoltage Lockout monitors the external
supply voltage VVCC. When the SMPS is plugged to the
main line the internal Startup Cell is biased and starts
to charge the external capacitor CVCC which is
connected to the VCC pin. This VCC charge current is
controlled to 0.9mA by the Startup Cell. When the VVCC
exceeds the on-threshold VCCon=18V the bias circuit
are switched on. Then the Startup Cell is switched off
by the Undervoltage Lockout and therefore no power
losses present due to the connection of the Startup Cell
to the Drain voltage. To avoid uncontrolled ringing at
switch-on, a hysteresis start up voltage is implemented.
The switch-off of the controller can only take place
when VVCC falls below 10.5V after normal operation
was entered. The maximum current consumption
before the controller is activated is about 150μA.
When VVCC falls below the off-threshold VCCoff=10.5V,
the bias circuit is switched off and the soft start counter
is reset. Thus it is ensured that at every startup cycle
the soft start starts at zero.
The internal bias circuit is switched off if Auto Restart
Mode is entered. The current consumption is then
reduced to 150μA.
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart
Mode does not require re-cycling the AC line.
When Active Burst Mode is entered, the internal Bias is
switched off most of the time but the Voltage Reference
is kept alive in order to reduce the current consumption
below 450μA.
3.3 Improved Current Mode
Soft-Start Comparator
FB
C8
0.67V
PWM OP
x3.3
Improved
Current Mode
Figure 4 Current Mode
PWM-Latch
RQ
Driver
SQ
CS
Current Mode means the duty cycle is controlled by the
slope of the primary current. This is done by comparing
the FB signal with the amplified current sense signal.
Amplified Current Signal
FB
0.67V
Driver
t
ton
t
Figure 5 Pulse Width Modulation
In case the amplified current sense signal exceeds the
FB signal the on-time Ton of the driver is finished by
resetting the PWM-Latch (see Figure 5).
The primary current is sensed by the external series
rCeosoislMtoOr RS®Se.nBseyinmseeartnesd
in
of
the source of
Current Mode
the integrated
regulation, the
secondary output voltage is insensitive to the line
variations. The current waveform slope will change with
the line variation, which controls the duty cycle.
The external RSense allows an individual adjustment of
the maximum source current of the integrated
CoolMOS®.
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
maximum duty cycle limitation the switch T2 is closed
by VOSC. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by
the inverted VOSC signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing VFB below that
threshold.
Version 2.1
9 19 Nov 2012

9 Page
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ICE3BR1065J transistor, igbt
4.3.2
Internal Voltage Reference
Parameter
Symbol
Trimmed Reference Voltage
VREF
CoolSET®-F3R
ICE3BR1065J
Electrical Characteristics
min.
4.90
Limit Values
typ. max.
5.00
5.10
Unit Test Condition
V measured at pin FB
IFB = 0
4.3.3
PWM Section
Parameter
Fixed Oscillator Frequency
Frequency Jittering Range
Frequency Jittering period
Max. Duty Cycle
Symbol
fOSC1
fOSC2
fjitter
Tjitter
Dmax
min.
56.5
59.8
-
-
0.70
Limit Values
typ. max.
65.0
73.5
65.0
70.2
±2.6
-
4.0 -
0.75
0.80
Min. Duty Cycle
Dmin
0-
-
PWM-OP Gain
AV 3.1 3.3 3.5
Voltage Ramp Offset
VOffset-Ramp
-
0.67
-
VFB Operating Range Min Level VFBmin
-
0.5 -
VFB Operating Range Max level VFBmax
-
-
4.3
FB Pull-Up Resistor
RFB
9
15.4
22
Unit
kHz
kHz
kHz
ms
V
V
V
kΩ
Test Condition
Tj = 25°C
Tj = 25°C
Tj = 25°C
VFB < 0.3V
CS=1V, limited by
Comparator C41)
1) The parameter is not subjected to production test - verified by design/characterization
4.3.4
Soft Start time
Parameter
Soft Start time
Symbol
tSS
min.
-
Limit Values
typ. max.
20.0
-
Unit Test Condition
ms
Version 2.1
21 19 Nov 2012

21 Page





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