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PDF 29EE512 Data sheet ( Hoja de datos )
| Número de pieza | 29EE512 | |
| Descripción | SST29EE512 | |
| Fabricantes | SST | |
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512 Kilobit (64K x8) Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
FEATURES:
• Single Voltage Read and Write Operations
– 5.0V-only for SST29EE512
– 3.0-3.6V for SST29LE512
– 2.7-3.6V for SST29VE512
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 512 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 2.5 sec (typical)
– Effective Byte-Write Cycle
Time: 39 µs (typical)
Data Sheet
• Fast Read Access Time
– 5.0V-only operation: 70 and 90 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
• Latched Address and Data
• Automatic Write Timing
– Internal VPP Generation
• End of Write Detection
– Toggle Bit
– Data# Polling
• Hardware and Software Data Protection
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32 Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 14mm, 8mm x 20mm)
PRODUCT DESCRIPTION
The SST29EE512/29LE512/29VE512 are 64K x8
CMOS, Page-Write EEPROMs manufactured with
SST’s proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and
thick oxide tunneling injector attain better reliability
and manufacturability compared with alternate ap-
proaches. The SST29EE512/29LE512/29VE512 write
with a single power supply. Internal Erase/Program is
transparent to the user. The SST29EE512/29LE512/
29VE512 conform to JEDEC standard pinouts for byte-
wide memories.
Featuring high performance Page-Write, the
SST29EE512/29LE512/29VE512 provide a typical
Byte-Write time of 39 µsec. The entire memory, i.e., 64
KBytes, can be written page-by-page in as little as 2.5
seconds, when using interface features such as
Toggle Bit or Data# Polling to indicate the completion
of a Write cycle. To protect against inadvertent write,
the SST29EE512/29LE512/29VE512 have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spec-
trum of applications, the SST29EE512/29LE512/
29VE512 are offered with a guaranteed Page-Write
endurance of 104 cycles. Data retention is rated at
greater than 100 years.
The SST29EE512/29LE512/29VE512 are suited for ap-
plications that require convenient and economical updat-
ing of program, configuration, or data memory. For all
system applications, the SST29EE512/29LE512/
29VE512 significantly improve performance and reliabil-
ity, while lowering power consumption. The
SST29EE512/29LE512/29VE512 improve flexibility
while lowering the cost for program, data, and configura-
tion storage applications.
To meet high density, surface mount requirements, the
SST29EE512/29LE512/29VE512 are offered in 32-pin
TSOP (8mm x 14mm and 8mm x 20mm) and 32-lead
PLCC packages. A 600-mil, 32-pin PDIP package is also
available. See Figures 1 and 2 for pinouts.
Device Operation
The SST Page-Mode EEPROM offers in-circuit electri-
cal write capability. The SST29EE512/29LE512/
29VE512 do not require separate Erase and Program
operations. The internally timed Write cycle executes
both erase and program transparently to the user. The
SST29EE512/29LE512/29VE512 have industry stan-
dard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE512/
29LE512/29VE512 are compatible with industry stan-
dard EEPROM pinouts and functionality.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
© 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
301-3 6/00
1
SSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
512 Kilobit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
A11
A9
A8
A13
A14
NC
WE#
VCC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP
32 OE#
31 A10
30 CE#
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 VSS
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
301 ILL F01.1
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6 32-Pin
7 PDIP
8 Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
4 3 2 1 32 31 30
5 29
6 28
7 27
8 32-Lead PLCC 26
9 25
10
Top View
24
11 23
12 22
13 21
14 15 16 17 18 19 20
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
301 ILL F02.0
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
A15-A7
Row Address Inputs
A6-A0
DQ7-DQ0
Column Address
Inputs
Data Input/output
CE#
OE#
WE#
Vcc
Chip Enable
Output Enable
Write Enable
Power Supply
Vss Ground
NC No Connection
Functions
To provide memory addresses. Row addresses define a page for
a Write cycle.
Column Addresses are toggled to load page data.
To output data during Read cycles and receive input data during Write
cycles. Data is internally latched during a Write cycle. The outputs are in
tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations
To provide 5-volt supply (± 10%) for the SST29EE512, 3-volt supply
(3.0-3.6V) for the SST29LE512, and 2.7-volt supply (2.7-3.6V) for the
SST29VE512
Unconnected pins.
301PGM T2.1
© 2000 Silicon Storage Technology, Inc.
5
301-3 6/00
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
5 Page 
512 Kilobit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS
Symbol
TWC
TAS
TAH
TCS
TCH
TOES
TOEH
TCP
TWP
TDS
TDH
TBLC(1)
TBLCO(1)
TIDA
TSCE
Parameter
Write Cycle (Erase and Program)
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
WE# Pulse Width
Data Setup Time
Data Hold Time
Byte Load Cycle Time
Byte Load Cycle Time
Software ID Access and Exit Time
Software Chip-Erase
SST29EE512
Min Max
10
0
50
0
0
0
0
70
70
35
0
0.05 100
200
10
20
SST29LE/VE512
Min Max
10
0
70
0
0
0
0
120
120
50
0
0.05 100
200
10
20
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ms
Note:
(1)This
parameter
is
measured
only
for
initial
qualification
and
after
the
design
or
process
change
that
could
affect
this
301 PGM T13.3
parameter.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
© 2000 Silicon Storage Technology, Inc.
11
301-3 6/00
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 29EE512.PDF ] | |
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