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Número de pieza MC95FG308
Descripción 8-BIT MICROCONTROLLERS
Fabricantes ABOV　
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No Preview Available ! MC95FG308 Hoja de datos, Descripción, Manual

MC95FG308
ABOV SEMICONDUCTOR Co., Ltd.
8-BIT MICROCONTROLLERS
MC95FG308
User’s Manual (Ver.2.9)
May 21, 2012 Ver.2.9
1

1 page




MC95FG308 pdf
MC95FG308
9.2.1 Data Register (Px) .............................................................................................................................. 56
9.2.2 Direction Register (PxIO) .................................................................................................................. 56
9.2.3 Pull-up Resistor Selection Register (PxPU) ....................................................................................... 56
9.2.4 Open-drain Selection Register (PxOD) .............................................................................................. 56
9.2.5 Debounce Enable Register (PxDB).................................................................................................... 56
9.2.6 Pin Change Interrupt Enable Register (PCI0) .................................................................................... 57
9.2.7 Port Selection Register (PSRx) .......................................................................................................... 57
9.2.8 Register Map ...................................................................................................................................... 57
9.3 Px Port ....................................................................................................................................................... 58
9.3.1 Px Port Description ............................................................................................................................ 58
9.3.2 Register description for Px................................................................................................................. 58
9.4 Port RESET Noise Canceller ..................................................................................................................... 60
10. Interrupt Controller......................................................................................................................................... 61
10.1 Overview.................................................................................................................................................. 61
10.2 External Interrupt ..................................................................................................................................... 62
10.3 Block Diagram......................................................................................................................................... 63
10.4 Interrupt Vector Table.............................................................................................................................. 64
10.5 Interrupt Sequence ................................................................................................................................... 64
10.6 Effective Timing after Controlling Interrupt bit ...................................................................................... 66
10.7 Multi Interrupt.......................................................................................................................................... 67
10.8 Interrupt Enable Accept Timing .............................................................................................................. 68
10.9 Interrupt Service Routine Address ........................................................................................................... 68
10.10 Saving/Restore General-Purpose Registers............................................................................................ 68
10.11 Interrupt Timing..................................................................................................................................... 69
10.12 Interrupt Register Overview................................................................................................................... 70
10.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3, IE4, IE5) ................................................................. 70
10.12.2 Interrupt Priority Register (IP, IP1)................................................................................................ 70
10.12.3 External Interrupt Flag Register (EIFLAG) ................................................................................... 70
10.12.4 External Interrupt Edge Register (EIEDGE) .................................................................................. 70
10.12.5 External Interrupt Polarity Register (EIPOLA).............................................................................. 70
10.12.6 External Interrupt Enable Register (EIENAB) ............................................................................... 70
10.12.7 External Interrupt Both Edge Enable Register (EIBOTH) ............................................................. 70
10.12.8 Register Map .................................................................................................................................. 71
10.13 Interrupt Register Description................................................................................................................ 71
10.13.1 Register description for Interrupt ................................................................................................... 71
11. Peripheral Hardware ....................................................................................................................................... 77
11.1 Clock Generator ....................................................................................................................................... 77
11.1.1 Overview.......................................................................................................................................... 77
11.1.2 Block Diagram ................................................................................................................................. 77
11.1.3 Register Map .................................................................................................................................... 78
11.1.4 Clock Generator Register description .............................................................................................. 78
11.1.5 Register description for Clock Generator......................................................................................... 78
11.2 BIT........................................................................................................................................................... 80
11.2.1 Overview.......................................................................................................................................... 80
11.2.2 Block Diagram ................................................................................................................................. 80
11.2.3 Register Map .................................................................................................................................... 80
May 21, 2012 Ver.2.9
5

5 Page





MC95FG308 arduino
MC95FG308
Figure 11-44 Sampling of Data and Parity Bit ................................................................................... 145
Figure 11-45 Stop Bit Sampling and Next Start Bit Sampling ........................................................... 146
Figure 11-46 SPI Clock Formats when UCPHA=0 ............................................................................ 147
Figure 11-47 SPI Clock Formats when UCPHA=1 ............................................................................ 148
Figure 11-48 SPI Block Diagram ....................................................................................................... 155
Figure 11-49 SPI Transmit/Receive Timing Diagram at CPHA = 0 .................................................. 157
Figure 11-50 SPI Transmit/Receive Timing Diagram at CPHA = 1 .................................................. 157
Figure 11-51 I2C Block Diagram........................................................................................................ 160
Figure 11-52 Bit Transfer on the I2C-Bus........................................................................................... 161
Figure 11-53 START and STOP Condition........................................................................................ 161
Figure 11-54 STOP or Repeated START Condition .......................................................................... 162
Figure 11-55 Acknowledge on the I2C-Bus ........................................................................................ 163
Figure 11-56 Clock Synchronization during Arbitration Procedure ................................................... 163
Figure 11-57 Arbitration Procedure of Two Masters.......................................................................... 164
Figure 11-58 Formats and States in the Master Transmitter Mode..................................................... 166
Figure 11-59 Formats and States in the Master Receiver Mode ......................................................... 168
Figure 11-60 Formats and States in the Slave Transmitter Mode....................................................... 170
Figure 11-61 Formats and States in the Slave Receiver Mode ........................................................... 172
Figure 11-62 ADC Block Diagram..................................................................................................... 177
Figure 11-63 A/D Analog Input Pin Connecting Capacitor................................................................ 178
Figure 11-64 A/D Power(AVDD) Pin Connecting Capacitor ............................................................ 178
Figure 11-65 ADC Operation for Align bit ........................................................................................ 178
Figure 11-66 Converter Operation Flow............................................................................................. 179
Figure 11-67 Analog Comparator Block Diagram.............................................................................. 183
Figure 12-1 IDLE Mode Release Timing by External Interrupt ......................................................... 187
Figure 12-2 IDLE Mode Release Timing by /RESET ........................................................................ 187
Figure 12-3 STOP Mode Release Timing by External Interrupt ........................................................ 188
Figure 12-4 STOP Mode Release Timing by /RESET ....................................................................... 188
Figure 12-5 STOP1, 2 Mode Release Flow ........................................................................................ 189
Figure 13-1 RESET Block Diagram ................................................................................................... 191
Figure 13-2 Reset noise canceller time diagram ................................................................................. 192
Figure 13-3 Fast VDD rising time ...................................................................................................... 192
Figure 13-4 Internal RESET Release Timing On Power-Up .............................................................. 193
Figure 13-5 Configuration timing when Power-on............................................................................. 193
Figure 13-6 Boot Process Waveform.................................................................................................. 194
Figure 13-7 Timing Diagram after RESET......................................................................................... 195
Figure 13-8 Oscillator generating waveform example........................................................................ 195
Figure 13-9 Block Diagram of BOD .................................................................................................. 196
Figure 13-10 Internal Reset at the power fail situation....................................................................... 196
Figure 13-11 Configuration timing when BOD RESET..................................................................... 197
Figure 14-1 Block Diagram of On-chip Debug System...................................................................... 200
Figure 14-2 10-bit transmission packet............................................................................................... 201
Figure 14-3 Data transfer on the twin bus........................................................................................... 201
May 21, 2012 Ver.2.9
11

11 Page







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