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PDF MKV31F512VLL12 Data sheet ( Hoja de datos )
| Número de pieza | MKV31F512VLL12 | |
| Descripción | KV31F Sub-Family Reference Manual | |
| Fabricantes | Freescale Semiconductor | |
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KV31F Sub-Family Reference Manual
Supports: MKV31F512VLL12, MKV31F512VLH12
Document Number: KV31P100M120SF7RM
Rev. 3, 7/2014
1 page  
Section number
Title
Page
3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................74
3.3.11 Watchdog Configuration..............................................................................................................................76
3.4 Clock modules..............................................................................................................................................................77
3.4.1 MCG Configuration.....................................................................................................................................77
3.4.2 OSC Configuration......................................................................................................................................79
3.5 Memories and memory interfaces.................................................................................................................................79
3.5.1 Flash Memory Configuration.......................................................................................................................79
3.5.2 Flash Memory Controller Configuration.....................................................................................................82
3.5.3 SRAM Configuration...................................................................................................................................83
3.5.4 System Register File Configuration.............................................................................................................84
3.5.5 EzPort Configuration...................................................................................................................................85
3.5.6 FlexBus Configuration.................................................................................................................................86
3.6 Security.........................................................................................................................................................................89
3.6.1 CRC Configuration......................................................................................................................................89
3.6.2 RNG Configuration......................................................................................................................................90
KV31F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
5
5 Page 
Section number
Title
Page
11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................228
11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................229
11.5.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................229
11.6 Functional description...................................................................................................................................................230
11.6.1 Pin control....................................................................................................................................................230
11.6.2 Global pin control........................................................................................................................................231
11.6.3 External interrupts........................................................................................................................................231
11.6.4 Digital filter..................................................................................................................................................232
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................235
12.1.1 Features........................................................................................................................................................235
12.2 Memory map and register definition.............................................................................................................................236
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................237
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................238
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................239
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................241
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................244
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................245
12.2.7 System Options Register 8 (SIM_SOPT8)..................................................................................................247
12.2.8 System Device Identification Register (SIM_SDID)...................................................................................249
12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................251
12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................253
12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................255
12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................258
12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................258
12.2.14 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................261
12.2.15 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................263
12.2.16 Unique Identification Register High (SIM_UIDH).....................................................................................264
KV31F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MKV31F512VLL12.PDF ] | |
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