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PDF MT29F1G16ABBEAHC Data sheet ( Hoja de datos )
| Número de pieza | MT29F1G16ABBEAHC | |
| Descripción | NAND Flash Memory | |
| Fabricantes | Micron Technology | |
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Micron Confidential and Proprietary
Preliminary‡
1Gb x8, x16: NAND Flash Memory
Features
NAND Flash Memory
MT29F1G08ABAEAWP-IT, MT29F1G08ABAEAWP, MT29F1G08ABAEAH4-IT
MT29F1G08ABAEAH4, MT29F1G08ABBEAH4-IT, MT29F1G08ABBEAH4,
MT29F1G16ABBEAH4-IT, MT29F1G16ABBEAH4, MT29F1G08ABBEAHC-IT,
MT29F1G08ABBEAHC, MT29F1G16ABBEAHC-IT, MT29F1G16ABBEAHC
Features
• Open NAND Flash Interface (ONFI) 1.0-compliant1
• Single-level cell (SLC) technology
• Organization
– Page size x8: 2112 bytes (2048 + 64 bytes)
– Page size x16: 1056 words (1024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
– Device size: 1Gb: 1024 blocks
• Asynchronous I/O performance
– tRC/tWC: 20ns (3.3V), 25ns (1.8V)
• Array performance
– Read page: 25µs
– Program page: 200µs (TYP, 3.3V and 1.8V)
– Erase block: 700µs (TYP)
• Command set: ONFI NAND Flash Protocol
• Advanced command set
– Program page cache mode
– Read page cache mode
– One-time programmable (OTP) mode
– Read unique ID
– Internal data move
– Block lock (1.8V only)
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Internal data move operations supported within the
device from which data is read
• Ready/busy# (R/B#) signal provides a hardware
method for detecting operation completion
• WP# signal: write protect entire device
• First block (block address 00h) is valid when ship-
ped from factory with ECC. For minimum required
ECC, see Error Management.
• Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-
cles are less than 1000
• RESET (FFh) required as first command after pow-
er-on
• Alternate method of device initialization (Nand_In-
it) after power up3 (contact factory)
• Quality and reliability
– Data retention: 10 years
– Endurance: 100,000 PROGRAM/ERASE cycles
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCC: 1.7–1.95V
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 48-pin TSOP type 1, CPL2
– 63-ball VFBGA
Notes:
1. The ONFI 1.0 specification is available at
www.onfi.org.
2. CPL = Center parting line.
3. Available only in the 1.8V VFBGA package.
PDF: 09005aef847d5585
m68m_non_ecc.pdf – Rev. E 7/12 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
1 page  
Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Features
List of Tables
Table 1: Asynchronous Signal Definitions ......................................................................................................... 8
Table 2: Array Addressing (x8) ........................................................................................................................ 16
Table 3: Array Addressing (x16) ...................................................................................................................... 17
Table 4: Asynchronous Interface Mode Selection ............................................................................................ 18
Table 5: Command Set .................................................................................................................................. 29
Table 6: READ ID Parameters for Address 00h ................................................................................................. 33
Table 7: READ ID Parameters for Address 20h ................................................................................................. 34
Table 8: Parameter Page Data Structure .......................................................................................................... 36
Table 9: Feature Address Definitions .............................................................................................................. 40
Table 10: Feature Address 90h – Array Operation Mode ................................................................................... 41
Table 11: Feature Addresses 01h: Timing Mode ............................................................................................... 43
Table 12: Feature Addresses 80h: Programmable I/O Drive Strength ................................................................ 44
Table 13: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 44
Table 14: Status Register Definition ................................................................................................................ 45
Table 15: Block Lock Address Cycle Assignments ............................................................................................ 64
Table 16: Block Lock Status Register Bit Definitions ........................................................................................ 67
Table 17: Error Management Details .............................................................................................................. 76
Table 18: Absolute Maximum Ratings ............................................................................................................. 77
Table 19: Recommended Operating Conditions .............................................................................................. 77
Table 20: Valid Blocks .................................................................................................................................... 77
Table 21: Capacitance .................................................................................................................................... 78
Table 22: Test Conditions ............................................................................................................................... 78
Table 23: AC Characteristics: Command, Data, and Address Input (3.3V) ......................................................... 79
Table 24: AC Characteristics: Command, Data, and Address Input (1.8V) ......................................................... 79
Table 25: AC Characteristics: Normal Operation (3.3V) ................................................................................... 80
Table 26: AC Characteristics: Normal Operation (1.8V) ................................................................................... 80
Table 27: DC Characteristics and Operating Conditions (3.3V) ........................................................................ 82
Table 28: DC Characteristics and Operating Conditions (1.8V) ........................................................................ 83
Table 29: ProgramErase Characteristics .......................................................................................................... 84
PDF: 09005aef847d5585
m68m_non_ecc.pdf – Rev. E 7/12 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
5 Page 
Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Signal Assignments
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View)
1 2 3 4 5 6 7 8 9 10
A NC NC
NC NC
B NC
NC NC
C WP# ALE VSS CE# WE# R/B#
D VCC RE# CLE NC NC NC
E NC NC NC NC NC NC
F NC NC NC NC VSS2 NC
G
DNU
VCC2 LOCK1 I/O13 I/O15 DNU
H I/O8 I/O0 I/O10 I/O12 I/O14 VCC
J I/O9 I/O1 I/O11 VCC I/O5 I/O7
K VSS I/O2 I/O3 I/O4 I/O6 VSS
L NC NC
NC NC
M NC NC
NC NC
Notes:
1. For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V de-
vice.
2. These pins might not be bonded in the package; however, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
PDF: 09005aef847d5585
m68m_non_ecc.pdf – Rev. E 7/12 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
11 Page | ||
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