STMP3620XXLAEB1M Datasheet PDF - Sigmatel
Part Number | STMP3620XXLAEB1M | |
Description | Audio System on Chip | |
Manufacturers | Sigmatel | |
Logo | ||
There is a preview and STMP3620XXLAEB1M download ( pdf file ) link at the bottom of this page. Total 30 Pages |
Preview 1 page No Preview Available ! PRODUCT DATA SHEET
STMP36xx
Audio System on Chip
with USB OTG, LCD, Hard Drive, and Battery Charger
Fourth-Generation Audio Decoder
Version 1.02 May 3, 2006
FM Tuner
Host Processor (Optional)
Rechargeable
Battery
LED/LCD/Color
Display
Hi-Speed USB
On-the-Go
Microphone
Voice Record
NAND Flash
SDRAM/NOR
SPDIF
Hard Drive
SD/SDIO/MS
Buttons/Switches
Headphones
ISO9001:2000 Certified
IEC QC 080000:2005
(IECQ HSPM) Certified
OFFICIAL PRODUCT DOCUMENTATION 5/3/06
5-36xx-D1-1.02-050306
Copyright © 2003-2006 SigmaTel, Inc.
All rights reserved.
SigmaTel, Inc. makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document, and makes
no commitment to update the information contained herein. SigmaTel reserves the right to change or discontinue this product at any time, without no-
tice. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuits based on information in this document.
The following are trademarks of SigmaTel, Inc., and may be used to identify SigmaTel products only: SigmaTel, the SigmaTel Logo, C Major, D Major
and Go-Chip. Windows Media and the Windows logo are trademarks or registered trademarks of Microsoft Corporation in the United States and/or
other countries. Other product and company names contained herein may be trademarks of their respective owners.
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OFFICIAL PRODUCT DOCUMENTATION 5/3/06
STMP36xx
7. DIGITAL CONTROL AND ON-CHIP RAM ................................................................................. 123
7.1. Overview ....................................................................................................................................... 123
7.2. SRAM Controls ............................................................................................................................. 124
7.2.1. SRAM BIST Control ........................................................................................................ 126
7.3. ROM Controls ............................................................................................................................... 127
7.4. Miscellaneous Controls ................................................................................................................. 127
7.4.1. Performance Monitoring .................................................................................................. 127
7.4.2. High-Entropy PRN Seed ................................................................................................. 127
7.4.3. Write-Once Register ........................................................................................................ 128
7.4.4. Microseconds Counter .................................................................................................... 128
7.5. Behavior During Reset .................................................................................................................. 128
7.6. Programmable Registers .............................................................................................................. 128
7.6.1. DIGCTL Control Register Description ............................................................................. 128
7.6.2. DIGCTL Status Register Description .............................................................................. 130
7.6.3. Free-Running HCLK Counter Register Description ......................................................... 131
7.6.4. On-Chip RAM Control Register Description .................................................................... 131
7.6.5. On-Chip RAM Repair Data 0 Register Description ......................................................... 133
7.6.6. On-Chip RAM Repair Data 1 Register Description ......................................................... 134
7.6.7. Software Write-Once Register Description ...................................................................... 135
7.6.8. AHB Transfer Count Register Description ...................................................................... 136
7.6.9. AHB Performance Metric for Stalled Bus Cycles Register Description ........................... 136
7.6.10. Entropy Register Description ........................................................................................ 137
7.6.11. Digital Control ROM Shield Read Enable Register Description .................................... 138
7.6.12. Digital Control Microseconds Counter Register Description ......................................... 138
7.6.13. Digital Control Debug Read Test Register Description ................................................. 139
7.6.14. Digital Control Debug Register Description ................................................................... 139
7.6.15. SRAM BIST Control and Status Register Description ................................................... 140
7.6.16. SRAM BIST Repair Register 0 Description ................................................................... 140
7.6.17. SRAM BIST Repair Register 1 Description ................................................................... 141
7.6.18. SRAM Status Register 0 Description ............................................................................ 142
7.6.19. SRAM Status Register 1 Description ............................................................................ 142
7.6.20. SRAM Status Register 2 Description ............................................................................ 143
7.6.21. SRAM Status Register 3 Description ............................................................................ 143
7.6.22. SRAM Status Register 4 Description ............................................................................ 144
7.6.23. SRAM Status Register 5 Description ............................................................................ 144
7.6.24. SRAM Status Register 6 Description ............................................................................ 145
7.6.25. SRAM Status Register 7 Description ............................................................................ 145
7.6.26. SRAM Status Register 8 Description ............................................................................ 146
7.6.27. SRAM Status Register 9 Description ............................................................................ 146
7.6.28. SRAM Status Register 10 Description .......................................................................... 147
7.6.29. SRAM Status Register 11 Description .......................................................................... 147
7.6.30. SRAM Status Register 12 Description .......................................................................... 148
7.6.31. SRAM Status Register 13 Description .......................................................................... 149
7.6.32. Digital Control Scratch Register 0 Description .............................................................. 150
7.6.33. Digital Control Scratch Register 1 Description .............................................................. 150
7.6.34. Digital Control ARM Cache Register Description .......................................................... 151
7.6.35. SigmaTel Copyright Identifier Register Description ....................................................... 151
7.6.36. Digital Control Chip Revision Register Description ....................................................... 152
8. USB HIGH-SPEED ON-THE-GO (HOST/DEVICE) CONTROLLER .......................................... 155
8.1. Overview ....................................................................................................................................... 155
8.2. USB Controller Core ..................................................................................................................... 155
8.3. USB Programmed I/O (PIO) Target Interface ............................................................................... 157
8.4. USB DMA Interface ....................................................................................................................... 157
8.5. USB UTMI Interface ...................................................................................................................... 157
8.5.1. Exporting the PHY ........................................................................................................... 157
8.5.2. Digital/Analog Loopback Test Mode ............................................................................... 157
8.6. USB Controller Flowcharts ............................................................................................................ 158
9. INTEGRATED USB 2.0 PHY ...................................................................................................... 161
9.1. Overview ....................................................................................................................................... 161
9.2. External Signals ............................................................................................................................ 161
9.3. UTMI and Digital Circuits .............................................................................................................. 162
5-36xx-D1-1.02-050306
Contents
5
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