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| Número de pieza | MC9S08GW64 | |
| Descripción | Microcontrollers | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08GW64
Rev. 3, 1/2011
MC9S08GW64 Series
Covers: MC9S08GW64 and
MC9S08GW6480-LQFP
Case 917A
64-LQFP
Case 840F
14 14
10 10
MC9S08GW32
8-Bit HCS08 Central Processor Unit (CPU)
comparator can be used as hardware breakpoint. Full mode,
Comparator A compares address and Comparator B compares data.
Supports both tag and force breakpoints
– New version of S08 core with same performace as traditional S08 and
lower power
– Up to 20 MHz CPU at 3.6 V to 2.15 V and up to 10 MHz CPU at 3.6 V
to 1.8 V, across temperature range of –40 C to 85 C
– HC08 instruction set with added BGND instruction
– Support for up to 48 interrupt/reset sources
On-Chip Memory
– Flash read/program/erase over full operating voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and flash
contents
Power-Saving Modes
– Two low power stop modes and reduced power wait mode
– Low power run and wait modes allow peripherals to run while voltage
regulator is in standby
– Peripheral clock gating register can disable clocks to unused modules,
thereby reducing currents
– Very low power external oscillator that can be used in stop2 or stop3
modes to provide accurate clock source to real time counter
– 6 s typical wakeup time from stop3 mode
Clock Source Options
– Oscillator (XOSC1) — Loop-control Pierce oscillator; Crystal or
ceramic resonator of 32.768 kHz; Clock source for iRTC or ICS
– Oscillator (XOSC2) — Loop-control Pierce oscillator; Crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz;
optional clock source for ICS
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal or
external reference (XOSC1, XOSC2); precision trimming of internal
reference allows 0.2% resolution and 2% deviation over temperature
and voltage; supporting CPU/bus frequencies from 1 MHz to 20 MHz
System Protection
– Watchdog computer operating properly (COP) reset with option to run
from dedicated 1 kHz internal clock source or bus clock
– Low-voltage warning with interrupt
– Low-voltage detection with reset or interrupt
– Illegal opcode and illegal address detection with reset
– Flash block protection
Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus 3 more breakpoints in breakpoint unit)
– Breakpoint (BKPT) debug module containing three comparators (A, B,
and C) with ability to match addresses in 64 KB space. Each
Peripherals
– LCD — up to 440 or 836 LCD driver with internal charge pump and
option to provide an internally regulated LCD reference that can be
trimmed for contrast control
– ADC16 — two analog-to-digital converters; 16-bit resolution; one
dedicated differential per ADC; up to 16-ch; up to 2.5 s conversion
time for 12-bit mode; automatic compare function; hardware
averaging; calibration registers; temperature sensor; internal bandgap
reference channel; operation in stop3; fully functional from 3.6 V to
1.8 V
– PRACMP —three rail to rail programmable reference analog
comparator; up to 8 inputs; on-chip programmable reference generator
output; selectable interrupt on rising, falling, or either edge of
comparator output; operation in stop3
– SCI — four full duplex non-return to zero (NRZ); LIN master extended
break generation; LIN slave extended break detection; wakeup on
active edge; SCI0 designed for AMR operation; TxD of SCI1 and SCI2
can be modulated with timers and RxD can recieved through
PRACMP;
– SPI— three full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first
shifting; SPI0 designed for AMR opeartion
– IIC — up to 100 kbps with maximum bus loading; multi-master
operation; programmable slave address; interrupt driven byte-by-byte
data transfer; supporting broadcast mode and 10-bit addressing;
supporting SM BUS functionality; can wake from stop3
– FTM — 2-channel flextimer module; selectable input capture, output
compare, or buffered edge- or center-aligned PWM on each channel
– IRTC — independent real-time clock, independent power domain, 32
bytes RAM, 32.768 kHz input clock optional output to ICS, hardware
calendar, hardware compensation due to crystal or temperature
characteristics, tamper detection and indicator
– PCRC — 16/32 bit programmable cyclic redundancy check for
high-speed CRC calculation
– MTIM — two 8-bit and one 16-bit timers; configurable clock inputs
and interrupt generation on overflow
– PDB — programmable delay block; optimized for scheduling ADC
conversions
– PCNT — position counter; working in stop3 mode without waking
CPU; can be used to generate waveforms like timer
Input/Output
– 57 GPIOs including one output-only pin
– Eight KBI interrupts with selectable polarity
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins.
Package Options
– 80-pin LQFP, 64-pin LQFP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2010-2011. All rights reserved.
1 page  
VDDA/VSSA
VREFH/VREFL
VREFO
VDD
VSS1
VSS2
BKGD/MS
RESETB
XTAL2
EXTAL2
XTAL1
EXTAL1
VBAT
TAMPER1
TAMPER2
VDDA/VSSA
VREFH/VREFL
AD[15]
ADC1
VDDA/VSSA
VREFH/VREFL
AD[15]
ADC0
Port A,F,G,H:
AD[15:2]
DADP/M[1]
trig[1]
sel[1]
trig[0]
sel[0]
Port A,F,G,H:
AD[15:2]
DADP/M[0]
VREG
PCRC
S08 Core V6
CPU
BKPT
INT
SIM
COP
LVD
FLASH
GW64 64 KB
GW32 32 KB
RAM
GW64 4 KB
GW32 2 KB
Internal Clock Source
REF CLK IRCLK
Clock Check & Select
XOSC2
XOSC1
CLKO
CLKO
Independent
RTC
The RTC is in a separate
power domain
PDB
trig[1:0]
sel[1:0]
KBI
Port A:
EXTRIG
Port B, D:
KBIP[7:0]
2-Channel FTM Port A, C, F:
FTMCH[0:1]
FTMCLK
16-bit MTIM3
Port A, F:
MTIMCLK
8-bit MTIM1
Port A, F:
MTIMCLK
8-bit MTIM2
Port A, F:
MTIMCLK
SPI0
SPI1
SPI2
IIC
SCI0
SCI1
SCI2
SCI3
Port B:
MOSI0 MISO0
SCLK0 SS0
Port C, G:
MOSI1 MISO1
SCLK1 SS1
Port A, D:
MOSI2 MISO2
SCLK2 SS2
Port A, B:
SDA
SCL
Port B:
RxD0
TxD0
Port B, C:
RxD1
TxD1
Port A, B:
RxD2
TxD2
Port C, G:
RxD3
TxD3
PRACMP0
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT0
PRACMP1
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT1
PRACMP2
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT2
PCNT
Port A, C, G, H:
PCNT0 PCNT1 PCNT2
PCNTCH0 PCNTCH1
LCD Port B, C, D, E, F, G, H:
LCD[0:43]
Devices in the MC9S08GW64 Series
PTA0/MOSI2/PCNTCH0/SCL/AD2
PTA1/MISO2/PCNTCH1/SDA/AD3
PTA2/SCLK2/FTMCH0/PCNT0/CMPP0
PTA3/SS2/FTMCH1/PCNT1/CMPP1
PTA4/MTIMCLK/RxD2/PCNT2/CMPP2
PTA5/FTMCLK/TxD2/EXTRIG/IRQ
PTA6/CMPOUT0/CLKOUT/BKGD/MS
PTB0/KBIP0/TxD1/EXTAL2
PTB1/KBIP1/RxD1/XTAL2
PTB2/KBIP2/MOSI0/MISO0/RxD0
PTB3/KBIP3/MISO0/MOSI0/TxD0
PTB4/KBIP4/SCLK0/SCL
PTB5/KBIP5/SS0/SDA
PTB6/KBIP6/RxD2/LCD0
PTB7/KBIP7/TxD2/LCD1
PTC0/MOSI1/LCD2
PTC1/MISO1/LCD3
PTC2/SCLK1/LCD4
PTC3/SS1/LCD5
PTC4/FTMCH0/RxD1/LCD6
PTC5/FTMCH1/TxD1/LCD7
PTC6/PCNTCH0/RxD3/LCD8
PTC7/PCNTCH1/TxD3/LCD9
PTD0/KBIP0/MOSI2/LCD10
PTD1/KBIP1/MISO2/LCD11
PTD2/KBIP2/SCLK2/LCD12
PTD3/KBIP3/SS2/LCD13
PTD4/KBIP4/LCD14
PTD5/KBIP5/CLKOUT/LCD15
PTD6/KBIP6/LCD16
PTD7/KBIP7/LCD17
PTE0/LCD18
PTE1/LCD19
PTE2/LCD20
PTE3/LCD21
PTE4/LCD22
PTE5/LCD23
PTE6/LCD24
PTE7/LCD25
PTF0/LCD26
PTF1/LCD27
PTF2/LCD28
PTF3/LCD29
PTF4/LCD30
PTF5/LCD31
PTF6/MTIMCLK/AD4/LCD32
PTF7/FTMCLK/AD5/LCD33
PTG0/MOSI1/AD6/LCD34
PTG1/MISO1/AD7/LCD35
PTG2/SCLK1/AD8/LCD36
PTG3/SS1/AD9/LCD37
PTG4/CMPOUT1/RxD3/AD10/LCD38
PTG5/CMPOUT2/TxD3/AD11/LCD39
PTG6/CMPP3/AD12/PCNT0/LCD40
PTG7/CMPP4/AD13/PCNT1/LCD41
PTH0/CMPP5/AD14/PCNT2/LCD42
PTH1/RTCCLKOUT/CMPP6/AD15/LCD43
Figure 1. MC9S08GW64 Series Block Diagram
Freescale Semiconductor
MC9S08GW64 Series MCU Data Sheet, Rev. 3
5
5 Page 
Electrical Characteristics
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +3.8
V
Maximum current into VDD
IDD 120 mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins except PTA5
and PTB1)1, 2, 3
ID
25 mA
Instantaneous maximum current
Single pin limit (applies to PTA5 and PTB1)1,2,3
ID
50 mA
Storage temperature range
Tstg
–55 to 150
C
1 Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to VSS and VDD.
3 Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine
the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Thermal Characteristics
Rating
Operating temperature range
(packaged)
Maximum junction temperature
Thermal resistance
Single-layer board
80-pin LQFP
64-pin LQFP
Thermal resistance
Four-layer board
80-pin LQFP
64-pin LQFP
Symbol
TA
TJ
JA
Value
TL to TH
–40 to 85
95
Unit
C
C
61 C/W
70
JA 48 C/W
52
Freescale Semiconductor
MC9S08GW64 Series MCU Data Sheet, Rev. 3
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MC9S08GW64.PDF ] | |
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