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PDF Si4734-D60 Data sheet ( Hoja de datos )
| Número de pieza | Si4734-D60 | |
| Descripción | BROADCAST AM/FM/SW/LW RADIO RECEIVER | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si4730/31/34/35-D60
BROADCAST AM/FM/SW/LW RADIO RECEIVER
Features
Worldwide FM band support
Seven selectable AM channel filters
(64–108 MHz)
AM/FM/SW/LW digital tuning
Worldwide AM band support
EN55020 compliant
(520–1710 kHz)
No manual alignment necessary
SW band support (Si4734/35)
Programmable reference clock
(2.3–26.1 MHz)
Adjustable soft mute control
LW band support (Si4734/35)
RDS/RBDS processor (Si4731/35)
(153–279 kHz)
Digital audio out
Excellent real-world performance 2-wire and 3-wire control interface
Integrated VCO
Integrated LDO regulator
Advanced AM/FM seek tuning
Wide range of ferrite loop sticks and
Automatic frequency control (AFC)
air loop antennas supported
Automatic gain control (AGC)
QFN and SSOP packages
Digital FM stereo decoder
RoHS compliant
Programmable de-emphasis
Advanced Audio Processing
Applications
Table and portable radios
Mini/micro systems
CD/DVD and Blu-ray players
Stereo boom boxes
Description
Modules for consumer electronics
Clock radios
Mini HiFi and docking stations
Entertainment systems
The Si473x-D60 digital CMOS AM/FM radio receiver IC integrates the complete
broadcast tuner and receiver function from antenna input to digital audio output.
The device leverages the Silicon Labs broadcast proven digital low-IF
architecture, enabling a cost-effective, digital audio platform for consumer
electronic applications with high TDMA noise immunity, superior radio
performance, and high fidelity audio power amplification.
Functional Block Diagram
FM / SW
ANT
FMI
AM / LW
ANT
AMI
RFGND
2.7~5.5 V (QFN)
2.0~5.5 V (SSOP) VA
+ GND
LNA
AGC
LNA
AGC
LDO
Mux
Mux
Si473x-D60
RDS
(S i4 7 3 1 /
35)
LOW -IF
D IG ITA L
A U D IO
DOUT
DFS
G P O /D C L K
ADC
DAC
DSP
ADC
DAC
ROUT
LOUT
AFC
CONTROL
IN T E R F A C E
VD
1.62 - 3.6 V
Ordering Information:
See page 31.
Pin Assignments
Si473x-D60 (QFN)
NC 1 20 19 18 17 16
FMI 2
15 DOUT
RFGND 3
AMI 4
GND
PAD
14 LOUT/[DFS]
13 ROUT/[DOUT]
RST 5
12 GND
6 7 8 9 10 11 VA
Si473x-D60(SSOP)
DOUT
DFS
GPO3/[DCLK]
GPO2/[INT]
GPO1
NC
NC
FMI
RFGND
NC
NC
AMI
1
2
3
4
5
6
7
8
9
10
11
12
24 LOUT/[DFS]
23 ROUT/[DOUT]
22 DBYP
21 VA
20 VD
19 RCLK
18 SDIO
17 SCLK
16 SEN
15 RST
14 GND
13 GND
This product, its features, and/or its
architecture is covered by one or more of
the following patents, as well as other
patents, pending and issued, both
foreign and domestic: 7,127,217;
7,272,373; 7,272,375; 7,321,324;
7,355,476; 7,426,376; 7,471,940;
7,339,503; 7,339,504.
Rev. 1.2 8/13
Copyright © 2013 by Silicon Laboratories
Si473x-D60
1 page  
Si4730/31/34/35-D60
1. Electrical Specifications
Table 1. Recommended Operating Conditions1
Parameter
Symbol Test Condition Min Typ Max Unit
Analog Supply Voltage
VA
2.72 —
5.5
V
Digital and I/O Supply Voltage
VD
1.62 — 3.6 V
Power Supply Powerup Rise Time
VDDRISE
10 — — µs
Interface Power Supply Powerup Rise Time
VIORISE
10 — — µs
Ambient Temperature
TA –20 25 85 C
Notes:
1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
VA = 3.3 V and 25 C unless otherwise stated.
2. SSOP devices operate down to 2 V at 25 °C. See section “4.23. 2 V Operation (SSOP Only)” for details.
Rev. 1.2
5
5 Page 
Si4730/31/34/35-D60
Table 6. Digital Audio Interface Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
DCLK Cycle Time
DCLK Pulse Width High
DCLK Pulse Width Low
DFS Set-up Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
DOUT Propagation Delay from DCLK Falling
Edge
Symbol Test Condition
tDCT
tDCH
tDCL
tSU:DFS
tHD:DFS
tPD:DOUT
Min
26
10
10
5
5
0
Typ Max Unit
— 1000 ns
— — ns
— — ns
— — ns
— — ns
— 50 ns
DCLK
DFS
DOUT
tDCH
tDCL
tDCT
tHD:DFS
tSU:DFS
tPD:OUT
Figure 6. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.2
11
11 Page | ||
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| PDF Descargar | [ Datasheet Si4734-D60.PDF ] | |
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