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ALC883DTS-GR PDF Datasheet - Realtek Microelectronics

Part Number ALC883DTS-GR
Description 7.1+2 CHANNEL HIGH DEFINITION AUDIO CODEC
Manufacturers Realtek Microelectronics 
Logo Realtek Microelectronics Logo 
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ALC883DTS-GR datasheet, circuit
ALC883-GR
ALC883D-GR
ALC883DTS-GR
ALC883DD-GR
7.1+2 CHANNEL HIGH DEFINITION AUDIO CODEC
DATASHEET
Rev. 1.1
22 August 2005
Track ID: JATR-1076-21

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ALC883DTS-GR pdf, schematic
ALC883 Series
Datasheet
COPYRIGHT
©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC883 Series Audio Codec ICs.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
1.1
Release Date
2005/08/02
2005/08/22
Summary
First release.
Update section 2.1 Hardware Features, page 2, section 9.1.1 Absolute
Maximum Ratings, page 61, and section 12 Ordering Information, page 70.
7.1+2 Channel High Definition Audio Codec
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ALC883DTS-GR equivalent
ALC883 Series
Datasheet
8.37. VERB – FUNCTION RESET (VERB ID=7FFH) ..................................................................................57
8.38. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH) ..............57
8.39. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ................59
9. Electrical Characteristics ......................................................................................... 61
9.1. DC CHARACTERISTICS ...................................................................................................................61
9.1.1. Absolute Maximum Ratings ..................................................................................................................................61
9.1.2. Threshold Voltage .................................................................................................................................................61
9.1.3. Digital Filter Characteristics ...............................................................................................................................62
9.1.4. S/PDIF Input/Output Characteristics...................................................................................................................62
9.2. AC CHARACTERISTIC .....................................................................................................................63
9.2.1. Link Reset and Initialization Timing.....................................................................................................................63
9.2.2. Link Timing Parameters at the Codec ..................................................................................................................64
9.2.3. S/PDIF Output and Input Timing .........................................................................................................................65
9.2.4. Test Mode..............................................................................................................................................................65
9.3. ANALOG PERFORMANCE ................................................................................................................66
10. Application Circuits .................................................................................................. 67
11. Mechanical Dimensions ............................................................................................ 68
11.1. MECHANICAL DIMENSIONS NOTES.................................................................................................69
12. Ordering Information ............................................................................................... 70
7.1+2 Channel High Definition Audio Codec
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ALC883DTS-GR diode, scr
ALC883 Series
Datasheet
1. General Description
The ALC883* series 7.1+2 Channel High Definition Audio (HDA) codecs are compliant with
Microsoft’s UAA (Universal Audio Architecture). The ALC883 series provide 10 DAC channels that
simultaneously support 7.1 sound playback, plus 2 channels of independent stereo sound output (multiple
streaming) through the front panel stereo output. Flexible mixing, mute, and fine gain control functions
provide a complete integrated audio solution for home entertainment PCs.
The ALC883 series also integrates two stereo ADCs that can support a stereo microphone with Acoustic
Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously.
All analog IO are input and output capable, and headphone amplifiers are also integrated at each analog
output. All analog IOs can be re-tasked according to user’s definitions, or automatically switched
depending on the connected device type.
The ALC883 supports 16/20/24 S/PDIF input and output to offer easy connection of PCs to high quality
consumer electronic products such as digital decoders and speakers.
The ALC883 series supports host/soft audio from the Intel ICH series chipset, and also from any other
HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent
software utilities like Karaoke mode, environment emulation, software equalizer, HRTF 3D positional
audio, and optional Dolby® Digital Live and DTS® CONNECTprogram, the ALC883 series provides
an excellent entertainment package and game experience for PC users.
*Note: The ALC883 series covers all products listed in section 12 Ordering Information, page 70.
7.1+2 Channel High Definition Audio Codec
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ALC883DTS-GR transistor, igbt
ALC883 Series
Datasheet
7.2.2. Outbound Frame – Multiple SDO
The HDA controller allows two SDO signals to be used to strip outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the ‘Strip Control’ bit in the controller’s Output Stream Control Register to initiate a
specific stream (Stream ‘A’ in Figure 9) to be transmitted on multiple SDOs. In this case, the MSB of
stream data is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a stripped stream. The codec does not support multiple SDOs connected to
SDO0.
To guarantee all codecs can determine their corresponding stream, the command stream is not stripped. It
is always transmitted on SDO0, and copied on SDO1.
SYNC
SDO0
Stream 'A' Tag
Frame SYNC
Stream 'A' to Codec A
Command Stream
...
Dn Dn-2
Stream 'X' Tag
Stream 'X' to Codec X
Stream 'Y' Tag
Stream 'Y' to Codec Y
SDO1
Command Stream
...
0s
Dn-1Dn-3 . . .
Stream A is "bit-stripped" on SDO0 and SDO1
Command Stream is unchanged, not stripped
0s
Figure 9. Stripped Stream on Multiple SDO
7.1+2 Channel High Definition Audio Codec
13
Track ID: JATR-1076-21 Rev. 1.1

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