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PDF DS0451 Data sheet ( Hoja de datos )
| Número de pieza | DS0451 | |
| Descripción | IGLOO2 FPGA and SmartFusion2 SoC FPGA | |
| Fabricantes | Microsemi | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS0451 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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IGLOO2 FPGA and SmartFusion2 SoC
FPGA
DS0451 Datasheet
1 page  
IGLOO2 FPGA and SmartFusion2 SoC FPGA
List of Figures
Figure 1. Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2. Input Buffer AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3. Output Buffer AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4. Tristate Buffer for Enable Path Test Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 5. Timing Model for Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 6. I/O Register Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 7. Timing Model for Output/Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 8. I/O Register Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 9. Input DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 10. Input DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 11. Output DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 12. Output DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 13. LUT-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 14. Sequential Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 15. Sequential Module Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 16. I2C Timing Parameter Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 17. SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1) . . . . . . . . . . . . . . . . . 122
Figure 18. SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1) . . . . . . . . . . . . . . . . . 127
Revision 5
5
5 Page 
Refer to Table 1 for Device Specific Status
IGLOO2 FPGA and SmartFusion2 SoC FPGA
IGLOO2 and SmartFusion2 SoC FPGA AC/DC Electrical
Characteristics
1. Introduction
Microsemi’s mainstream SmartFusion®2 SoC and IGLOO®2 FPGA families integrate an industry standard 4-input
lookup table-based (LUT) FPGA fabric with integrated mathblocks, multiple embedded memory blocks, and high-
performance SERDES communications interfaces on a single chip. Both families benefit from low power flash
technology and are the most secure and reliable FPGAs in the industry. These next generation devices offer up to
150K Logic Elements, up to five MB of embedded RAM, up to 16 SERDES lanes, and up to four PCI Express Gen 2
endpoints, as well as integrated hard DDR3 memory controllers with error correction.
SmartFusion2 devices integrate an entire low power real time Microcontroller Subsystem with a rich set of Industry
standard peripherals including Ethernet, USB, and CAN, while IGLOO2 devices integrate a high-performance memory
subsystem with on-chip flash, 32 Kbyte embedded SRAM, and multiple DMA controllers.
2. Device Status
For more information on device status, refer to the "Datasheet Categories" section on page 130.
Table 1 • IGLOO2 FPGA and SmartFusion2 SoC FPGA Device Status
Design Security Device Densities
005
010, 010T
025, 025T
050, 050T
060, 060T
090, 090T
150, 150T
Data Security Device Densities
005S
010TS
025TS
050TS
060TS
090TS
150TS
Status
Production
Production
Production
Production
Preliminary
Production
Preliminary
Status
Production
Production
Production
Production
Preliminary
Production
Preliminary
Revision 5
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS0451.PDF ] | |
Hoja de datos destacado
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