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PDF MT8870D Data sheet ( Hoja de datos )
| Número de pieza | MT8870D | |
| Descripción | Integrated DTMF Receiver | |
| Fabricantes | Mitel | |
| Logotipo |  |
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ISO2-CMOS MT8870D/MT8870D-1
®
Integrated DTMF Receiver
Features
• Complete DTMF Receiver
• Low power consumption
• Internal gain setting amplifier
• Adjustable guard time
• Central office quality
• Power-down mode
• Inhibit mode
• Backward compatible with
MT8870C/MT8870C-1
Applications
• Receiver system for British Telecom (BT) or
CEPT Spec (MT8870D-1)
• Paging systems
• Repeater systems/mobile radio
• Credit card systems
• Remote control
• Personal computers
• Telephone answering machine
ISSUE 3
May1995
Ordering Information
MT8870DE/DE-1 18 Pin Plastic DIP
MT8870DC/DC-1 18 Pin Ceramic DIP
MT8870DS/DS-1 18 Pin SOIC
MT8870DN/DN-1 20 Pin SSOP
MT8870DT/DT-1 20 Pin TSSOP
-40 °C to +85 °C
Description
The MT8870D/MT8870D-1 is a complete DTMF
receiver integrating both the bandsplit filter and
digital decoder functions. The filter section uses
switched capacitor techniques for high and low
group filters; the decoder uses digital counting
techniques to detect and decode all 16 DTMF tone-
pairs into a 4-bit code. External component count is
minimized by on chip provision of a differential input
amplifier, clock oscillator and latched three-state bus
interface.
VDD VSS
VRef
INH
PWDN
Bias
Circuit
Chip Chip
Power Bias
IN + Dial
Tone
IN - Filter
GS
VRef
Buffer
High Group
Filter
Zero Crossing
Detectors
Low Group
Filter
Digital
Detection
Algorithm
Code
Converter
and Latch
to all
Chip
Clocks
St Steering
GT Logic
OSC1
OSC2
St/GT
ESt
Figure 1 - Functional Block Diagram
STD
TOE
Q1
Q2
Q3
Q4
4-11
1 page  
ISO2-CMOS MT8870D/MT8870D-1
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will power down
the device to minimize the power consumption in a
standby mode. It stops the oscillator and the
functions of the filters.
Inhibit mode is enabled by a logic high input to the
pin 5 (INH). It inhibits the detection of tones
representing characters A, B, C, and D. The output
code will remain the same as the previous detected
code (see Table 1).
Differential Input Configuration
The input arrangement of the MT8870D/MT8870D-1
provides a differential-input operational amplifier as
well as a bias source (VRef) which is used to bias the
inputs at mid-rail. Provision is made for connection of
a feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
the input pins are connected as shown in Figure 10
with the
biasing
op-amp connected for unity
the input at 1/2VDD. Figure
gain and VRef
6 shows the
differential configuration, which permits the
adjustment of gain with the feedback resistor R5.
Crystal Oscillator
The internal clock circuit is completed with the
addition of an external 3.579545 MHz crystal and is
normally connected as shown in Figure 10 (Single-
Ended Input Configuration). However, it is possible
to configure several MT8870D/MT8870D-1 devices
employing only a single oscillator crystal. The
oscillator output of the first device in the chain is
coupled through a 30 pF capacitor to the oscillator
input (OSC1) of the next device. Subsequent devices
are connected in a similar fashion. Refer to Figure 7
for details. The problems associated with
unbalanced loading are not a concern with the
arrangement shown, i.e., precision balancing
capacitors are not required.
C1 R1
MT8870D/
IN+ MT8870D-1
+
-
IN-
C2 R4
R3
R5 GS
R2
VRef
Differential Input Amplifier
C1=C2=10 nF
RR12==6R04k=ΩR,5=R130=037k.Ω5 kΩ
All resistors are ±1% tolerance.
All capacitors are ±5% tolerance.
R3= R2R5
R2+R5
VOLTAGE
GAIN (Av diff)=
R5
R1
INPUT IMPEDANCE
(ZINDIFF) = 2
R12+
1
ωc
2
Figure 6 - Differential Input Configuration
OSC1
X-tal
To OSC1 of next
C MT8870D/MT8870D-1
OSC2
OSC2
C
OSC1
C=30 pF
X-tal=3.579545 MHz
Figure 7 - Oscillator Connection
Parameter Unit Resonator
R1
Ohms
10.752
L1 mH .432
C1 pF 4.984
C0 pF 37.915
Qm - 896.37
∆f % ±0.2%
Table 2. Recommended Resonator Specifications
Note: Qm=quality factor of RLC model, i.e., 1/2ΠƒR1C1.
4-15
5 Page 
ISO2-CMOS MT8870D/MT8870D-1
EVENTS
Vin
ESt
St/GT
Q1-Q4
StD
TOE
tREC
A
D
B CE
tREC
tID
tDO
TONE #n
TONE
#n + 1
tDP AAAAAAAA tDA
tGTP
tGTA
F
TONE
#n + 1
G
tPQ
DECODED TONE # (n-1)
tPSrD
tQStD
#n
HIGH IMPEDANCE
# (n + 1)
tPTD
tPTE
VTSt
EXPLANATION OF EVENTS
A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED.
B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS
C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMIAN LATCHED UNTIL NEXT VALID
TONE.
D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE.
E) TONE #n + 1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY
HIGH IMPEDANCE).
F) ACCEPTABLE DROPOUT OF TONE #n + 1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED.
G) END OF TONE #n + 1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT
VALID TONE.
EXPLANATION OF SYMBOLS
Vin DTMF COMPOSITE INPUT SIGNAL.
ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
Q1-Q4
StD
4-BIT DECODED TONE OUTPUT.
DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL.
TOE
tREC
tRE C
tID
tDO
tDP
tDA
tGTP
tGTA
TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q1-Q4 TO ITS HIGH IMPEDANCE STATE.
MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION
MAXIMUM TIME BETWEEN VALID DTMF SIGNALS.
MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL.
TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS.
TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.
GUARD TIME, TONE PRESENT.
GUARD TIME, TONE ABSENT.
Figure 11 - Timing Diagram
4-21
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MT8870D.PDF ] | |
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