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PDF SN9P701F-004 Data sheet ( Hoja de datos )
| Número de pieza | SN9P701F-004 | |
| Descripción | OPTICAL ID IMAGE Decoder | |
| Fabricantes | SONiX | |
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松翰科技股份有限公司
SONiX TECHNOLOGY CO., LTD.
Preliminary
SN9P701F-00X
OPTICAL ID IMAGE Decoder [ 2nd generation ]
- two_wire_interface version
1. General Description
SN9P701F is the second generation of OID decoder. It is designed for implementing
SONiX newly developed D.H.R.T. Technology (Data Hiding & Retrieving
Technology), which integrates the solution that includes CMOS sensor interface, image
pattern recognizing engine, voltage regulator, RC oscillator and retrieved index output
interface.
2. Feature of SN9P701F
- Support dot pattern format : OID_Code_v2
- Core voltage operation range : 3.0V ~ 3.6V ( Reference design )
- Regulator input : 3.6V ~5.0V ( Reference design )
- Low power dissipation : 3mA (typ)
- Shot down current : <10uA
- Embedded 16 bit-DSP for sensor control and image pattern recognition
- Light source timing control
- Built-in voltage regulator
- Built-in 16Mhz RC type oscillator ( not recommended in RF/IR version )
- Built-in low battery detection
- Bi-directions communication in two wire serial interface
- Output Optical_ID in two_wire_serial_interface
( Please refer to two_wire_interface_v2.pdf )
- 48 pin LQFP package.
3. Feature of OID_Code_V2
OID_Code_V2 is the 2nd generation of dot pattern used in OID system.
- Dimension of single dot pattern : 1.3mm x 1.3mm
- Number of index : 65,536（can extend to 262,144）
- Low visual artifact
- Low visual fixed pattern noise
- Suggested paper type :art coated paper, mid-grade paper*
1
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
SONiX TECHNOLOGY CO., LTD.
E-mail: [email protected]
V1.02 , Jul. 2006
1 page  
松翰科技股份有限公司
SONiX TECHNOLOGY CO., LTD.
Preliminary
SN9P701F-00X
6. Pin Assignment
LQFP
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PIN NAME Type
Description
KEY1
GPIO0
GPIO1
GPIO2
VDD3
GND
GPIO3
ADIO2
ADIO0
VSSD_OSC
RC_BIAS
VDD_OSC
XIN
XOUT
XTAL_SEL
VDD3
GND
TAVSS
DN
DP
TAVDD
VRO_S
VRO_P
GND_A
REG_IN
REG_EN
PWR_CTL
VDD5D
ADIO1
USB_DET
I KEY1 input（internal pull down）, connect to ground if no used
B General purpose I/O
B General purpose I/O
B General purpose I/O
P Digital VDD, 3.3V
P Digital ground
B General purpose I/O
B ADIO2/ADO_SDIO/IR_TRAN/RF_TRAN
B ADIO0/ADO_CLK
P GND for oscillator
RC oscillator bias, using an external “R” to set frequency.
P
Recommended “R” = 29KΩ±1% for 16MHz ±10% frequency.
P VDD for oscillator, 3.3V
I Crystal OSC input
B Crystal OSC output
I OSC type selection ( 1:Crystal, 0:RC )
P Digital VDD, 3.3V
P GND for I/O and core
P Reserved, please connect to digital GND
B Reserved, please connect 5KΩ to digital GND
B Reserved, please connect 5KΩ to digital VDD, 3.3V
P Reserved, please connect to digital VDD, 3.3V
O Regulator 3.3 v switch output, controlled by internal firmware
O Regulator 3.3 v output, controlled by REG_EN
P Analog ground
P Regulator input , 3.6V~5V
I Regulator enable
O Output for power control
P Digital VDD, VDD3 ~ 5V, please do not connect to VRO_P
B ADIO1/ADO_SCK
I Reserved, please connect to ground
5
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
SONiX TECHNOLOGY CO., LTD.
E-mail: [email protected]
V0.1 , JAN. 2003
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet SN9P701F-004.PDF ] | |
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