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PDF ES8396 Data sheet ( Hoja de datos )
| Número de pieza | ES8396 | |
| Descripción | Low Power Stereo Audio CODEC | |
| Fabricantes | Everest Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ES8396 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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ES8396
Low Power Stereo Audio CODEC
FEATURES
System
• High performance and low power multi-
bit delta-sigma stereo ADC and DAC
• Two independent I2S/PCM master or
slave serial data port
• Three pairs of analog input
• Four pairs of analog output
• 2x0.9W stereo or 1.8W mono class D
speaker driver
• Ground centered headphone driver
• Mono ear speaker driver
• 256/384Fs, USB 12/24 MHz, fractional
PLL for wide range of system clocks
• Sophisticated analog input and output
routing, mixing and gain
• Support analog and digital microphone
• GPIO
• I2C interface
ADC
• 24-bit, 8 to 96 kHz sampling frequency
• 95 dB dynamic range, 95 dB signal to
noise ratio, -85 dB THD+N
• Low noise pre-amplifier
• Auto level control (ALC) and noise gate
• Microphone bias
DAC
• 24-bit, 8 to 96 kHz sampling frequency
• 95 dB dynamic range, 95 dB signal to
noise ratio, -85 dB THD+N
• Digital peak limiter (DPL)
• Pop and click noise suppression
DSP
• Flexible digital signal routing and mixing
• Asynchronous sample rate conversion
• Six programmable digital filters for PEQ
and noise reduction
• Stereo enhancement
• Support u/A law
Low Power
• 1.8V to 3.3V operation
• 7 mW playback; 16 mW playback and
record
APPLICATIONS
• MID/Phoblet
• Smart Phone
• Digital amplifier
ORDERING INFORMATION
ES8396 -40°C ~ +85°C
QFN-48
1
1 page  
Everest Semiconductor
Confidential
3. TYPICAL APPLICATION CIRCUIT
ES8396
SPK_GND
AGND
DGND
VP_DUT
10K
I2CA0
VP_DUT
10K 10K
VSPK_DUT(+5V)
10uF 0.1uF 10uF 0.1uF
SPK_GND
10uF 0.1uF
SPK_GND
SPK_GND
I2C_SDA
I2C_SCL
VP_DUT(+1.8V- +3.3V)
DGND
VD_DUT(+1.8V- +3.3V)
10uF
10uF
DGND
I2S1_ALRCK_GPIO
I2S1_DACDAT
I2S1_ADCDAT
I2S1_BCLK
I2S1_LRCK
0.1uF
MCLK
I2S2_ALRCK
0.1uF
0
I2CA0
0
1
2
3
4
5
6
7
8
9
10
11
12
ADCLRCK/GPIO
DACDAT1
ADCDAT1
BCLK1
LRCK1
SDA
SCL
DPVDD
DGND
DCVDD
MCLK
ADCLRCK2/GPIO
ES8396
1nF 1nF
SPK_GND
1nF 1nF
SPK_GND
SPKR_P
8OHMRSPEAKER
SPKR_N
SPKL_N
8OHMLSPEAKER
SPKL_P
VP_DUT
10K
HPDETECT
HP_L
HP_R
5
4
3
2
6
1
Headphone
AGND
CPVSSP
CPTOP
CPVDD
DACVRP
MONOOUTN
MONOOUTP
AVDDLDO
AVDD
AGND
VMID
ADCVRP
MICN
0.1uF 10uF
AGND
33
330.01uF 0.01uF
MOUT_N
Receiverearpiece
MOUT_P
36 0.1uF 10uF
35
34 AGND
33
32
31
30
29
28
27
AGND
26
25 10uF
10uF 0.1uF
AGND
AGND
0.1uF
10uF 0.1uF
AGND
VCP_DUT(+1.8V)
10uFAGND
VA_DUT(+3.3V)
0.1uF 0.1uF 10uF
AGND
ROUT_N
LOUT_P
I2S2_SCLK
I2S2_LRCK
I2S2_DACDAT
I2S2_ADCDAT
10K 10K MONOIN_P
MONOIN_N
AIN_R
AGND
AIN_L
4.7uF
4.7uF
4.7uF
4.7uF
4.7uF
4.7uF
4.7uF 0.1uF
AGND
AGND
10uF 0.1uF
4.7uF
4.7uF
MICBIAS
2.2K
MICROPHONE
2.2K
AGND
Revision 2.0
5
June 2014
5 Page 
Everest Semiconductor
Confidential
LRCK duty cycle
SCLK frequency
SCLK pulse width low
SCLK Pulse width high
SCLK falling to LRCK edge
SCLK falling to SDOUT valid
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
TSCLKL
TSCLKH
TSLR
TSDO
TSDIS
TSDIH
40 60
26
15
15
–10 10
0
10
10
ES8396
%
MHz
ns
ns
ns
ns
ns
ns
Figure 8 Serial Audio Port Timing
I2C SWITCHING SPECIFICATIONS
PARAMETER
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL
Fall Time SCL
Symbol
FSCL
TTWID
TTWSTH
TTWCL
TTWCH
TTWSTS
TTWDH
TTWDS
TTWR
TTWF
MIN MAX UNIT
100 KHz
4.7 us
4.0 us
4.0 us
4.0 us
4.7 us
0.1 us
100 ns
25 us
25 ns
Revision 2.0
11
June 2014
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ES8396.PDF ] | |
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