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PDF TRD16P102B Data sheet ( Hoja de datos )
| Número de pieza | TRD16P102B | |
| Descripción | 48K Embedded OTP ROM Hi-Performance 16-bit Multimedia Processor | |
| Fabricantes | TRITAN TECHNOLOGY | |
| Logotipo |  |
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TRD16P102B
Data Sheet
V1.2
48K Embedded OTP ROM
Hi-Performance 16-bit Multimedia Processor
TRITAN TECHNOLOGY INC.
Preliminary Specification / V1.2 2010.08.16
1 page  
3. Application Field
‧PDA
‧Electronic Dictionary
‧Electronic Learning Aid (ELA)
‧Electronics storybook
4. Block Diagram
RSTBIN
TRD16P102B
16-bit Multimedia Processor
WDT Timer
RCOSC RTC
Interrupt Arbiter
TxP16
Core
MAC
SRAM
3Kx16
OTP ROM
48Kx16
GPIO
11-bit
PWMX2
or
12-bit
PWMX1
LVR
LChP
RChN
PortA
PortB
TRITAN TECHNOLOGY INC.
3 Preliminary Specification / V1.2 2010.08.16
5 Page 
TRD16P102B
16-bit Multimedia Processor
to store the index of interrupt service routine (ISR) address. User can access Interrupt Vector Table by read/write
IntVect I/O register.
Figure 5.4 Interrupt Vector Structure
5.4.2 Interrupt Controller
Common I/O registers
Symbol
STATUS
INTENA
INTREQ
Adr Reset RW B7 B6
00H 00 R/W INTEN
01H 00 R/W ENA7 ENA6
02H 00 R/W Req7 Req6
B5
ENA5
Req5
B4
ENA4
Req4
B3
AN
ENA3
Req3
B2
AV
ENA2
Req2
B1
AC
ENA1
Req1
B0
AZ
ENA0
Req0
Description
System Status Flag
Int Enable
Int Request
This chip provides 8 interrupt sources, user’s program can control 8 interrupts, including 6 internal PWM
Timer, Timer1, Timer2, RTC Timer and PC Stack Overflow interrupts, and 2 external ExtINT0, ExtINT1, interrupts.
More details control will describe as follows:
Interrupt Source
Interrupt Vector Priority
PWM Timer
0H INT0_IRQ
Timer1
1H INT1_IRQ
Timer2
2H INT2_IRQ
RTC Timer
3H INT3_IRQ
ExtINT0 Port A.b6
4H INT4_IRQ
ExtINT1 Port A.b7
5H INT5_IRQ
Reserve
6H INT6_IRQ
PC Stack Overflow
7H INT7_IRQ
Table 5.2 TRD16P102B Interrupt Sources
(a) Global interrupt enable(INTEN)
The global interrupt INTEN controls the enable/disable of all interrupts. When INTEN is cleared to “0”, all
interrupts are disabled. When INTEN is set to “1”, all interrupts are enabled (but still dependent on value of INTENA
register). The INTEN is initialized to ‘”0” after power on
(b) Interrupt enable (INTENA)
The interrupt enable ENA0, ENA1, ENA2, ENA3, ENA4, ENA5, ENA6, ENA7 are shown in above. An
interrupt is allowed when these control bit are set to “1”, and interrupt is inhibit when these control bit are cleared to
“0”. They are all initialized to “0” after power on.
TRITAN TECHNOLOGY INC.
9 Preliminary Specification / V1.2 2010.08.16
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