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PDF LAN8710A Data sheet ( Hoja de datos )

Número de pieza LAN8710A
Descripción Small Footprint MII/RMII 10/100 Ethernet Transceiver
Fabricantes SMSC　
Logotipo SMSC Logotipo




1. LAN8710A Transceiver






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LAN8710A/LAN8710Ai
Small Footprint MII/RMII 10/100 Ethernet
Transceiver with HP Auto-MDIX and
flexPWR® Technology
PRODUCT FEATURES
Datasheet
Highlights
„ Single-Chip Ethernet Physical Layer Transceiver
(PHY)
„ Comprehensive flexPWR® Technology
— Flexible Power Management Architecture
— LVCMOS Variable I/O voltage range: +1.6V to +3.6V
— Integrated 1.2V regulator with disable feature
„ HP Auto-MDIX support
„ Small footprint 32-pin QFN lead-free RoHS compliant
package (5 x 5 x 0.9mm height)
Target Applications
„ Set-Top Boxes
„ Networked Printers and Servers
„ Test Instrumentation
„ LAN on Motherboard
„ Embedded Telecom Applications
„ Video Record/Playback Systems
„ Cable Modems/Routers
„ DSL Modems/Routers
„ Digital Video Recorders
„ IP and Video Phones
„ Wireless Access Points
„ Digital Televisions
„ Digital Media Adaptors/Servers
„ Gaming Consoles
„ POE Applications (Refer to SMSC Application Note 17.18)
Key Benefits
„ High-Performance 10/100 Ethernet Transceiver
— Compliant with IEEE802.3/802.3u (Fast Ethernet)
— Compliant with ISO 802-3/IEEE 802.3 (10BASE-T)
— Loop-back modes
— Auto-negotiation
— Automatic polarity detection and correction
— Link status change wake-up detection
— Vendor specific register functions
— Supports both MII and the reduced pin count RMII
interfaces
„ Power and I/Os
— Various low power modes
— Integrated power-on reset circuit
— Two status LED outputs
— Latch-Up Performance Exceeds 150mA per EIA/JESD
78, Class II
— May be used with a single 3.3V supply
„ Additional Features
— Ability to use a low cost 25Mhz crystal for reduced BOM
„ Packaging
— 32-pin QFN (5x5 mm) Lead-Free RoHS Compliant
package with MII and RMII
„ Environmental
— Extended commercial temperature range
(0°C to +85°C)
— Industrial temperature range version available
(-40°C to +85°C)
SMSC LAN8710A/LAN8710Ai
DATASHEET
Revision 1.4 (08-23-12)

1 page




LAN8710A pdf
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
List of Figures
Figure 1.1 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1.2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2.1 32-QFN Pin Assignments (TOP VIEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.1 100BASE-TX Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3.2 100BASE-TX Receive Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3.3 Relationship Between Received Data and Specific MII Signals . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3.4 Direct Cable Connection vs. Cross-over Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 3.5 MDIO Timing and Frame Structure - READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3.7 LED1/REGOFF Polarity Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3.8 LED2/nINTSEL Polarity Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3.9 Near-end Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.10 Far Loopback Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.11 Connector Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3.12 Simplified System Level Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3.13 Power Supply Diagram (1.2V Supplied by Internal Regulator) . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 3.14 Power Supply Diagram (1.2V Supplied by External Source) . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 3.15 Twisted-Pair Interface Diagram (Single Power Supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 3.16 Twisted-Pair Interface Diagram (Dual Power Supplies). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 5.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 5.2 Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 5.3 Power-On nRST & Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 5.4 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 5.5 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 5.6 RMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 5.7 SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 6.1 32-QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 6.2 Recommended PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 6.3 Taping Dimensions and Part Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 6.4 Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 6.5 Tape Length and Part Quantity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SMSC LAN8710A/LAN8710Ai
5
DATASHEET
Revision 1.4 (08-23-12)

5 Page





LAN8710A arduino
NUM PINS
NAME
Receive
Data 0
PHY
Operating
1 Mode 0
Configuration
Strap
Receive
Data 1
PHY
Operating
1 Mode 1
Configuration
Strap
Receive
Data 2
(MII Mode)
MII/RMII
Mode Select
1 Configuration
Strap
Receive
Data 3
(MII Mode)
PHY Address
2
1 Configuration
Strap
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
Table 2.1 MII/RMII Signals (continued)
SYMBOL
RXD0
MODE0
RXD1
MODE1
RXD2
RMIISEL
RXD3
PHYAD2
BUFFER
TYPE
DESCRIPTION
VO8
Bit 0 of the 4 (2 in RMII Mode) data bits that are
sent by the transceiver on the receive path.
VIS
(PU)
VO8
Combined with MODE1 and MODE2, this
configuration strap sets the default PHY mode.
See Note 2.1 for more information on
configuration straps.
Note:
Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for
additional details.
Bit 1 of the 4 (2 in RMII Mode) data bits that are
sent by the transceiver on the receive path.
VIS
(PU)
Combined with MODE0 and MODE2, this
configuration strap sets the default PHY mode.
See Note 2.1 for more information on
configuration straps.
Note:
Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for
additional details.
VO8
VIS
(PD)
VO8
Bit 2 of the 4 (in MII Mode) data bits that are sent
by the transceiver on the receive path.
Note: This signal is not used in RMII Mode.
This configuration strap selects the MII or RMII
mode of operation. When strapped low to VSS,
MII Mode is selected. When strapped high to
VDDIO RMII Mode is selected.
See Note 2.1 for more information on
configuration straps.
Note:
Refer to Section 3.7.3, "RMIISEL:
MII/RMII Mode Configuration," on
page 37 for additional details.
Bit 3 of the 4 (in MII Mode) data bits that are sent
by the transceiver on the receive path.
Note: This signal is not used in RMII Mode.
VIS
(PD)
Combined with PHYAD0 and PHYAD1, this
configuration strap sets the transceiver’s SMI
address.
See Note 2.1 for more information on
configuration straps.
Note:
Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration," on
page 36 for additional information.
SMSC LAN8710A/LAN8710Ai
11
DATASHEET
Revision 1.4 (08-23-12)

11 Page







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