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PDF PTFB182503EL Data sheet ( Hoja de datos )

Número de pieza PTFB182503EL
Descripción Thermally-Enhanced High Power RF LDMOS FETs
Fabricantes Infineon Technologies 
Logotipo Infineon Technologies Logotipo



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PTFB182503EL
PTFB182503FL
Thermally-Enhanced High Power RF LDMOS FETs
240 W, 1805 – 1880 MHz
Description
The PTFB182503EL and PTFB182503FL are 240-watt LDMOS FETs
intended for use in multi-standard cellular power amplifier applications
in the 1805 to 1880 MHz frequency band. Features include input
and output matching, high gain, wide signal bandwidth and reduced
memory effects for improved DPD correctability. Manufactured with
Infineon's advanced LDMOS process, these devices provide excellent
thermal performance and superior reliability.
PTFB182503EL
H-33288-6
PTFB182503FL
H-34288-4/2
Two-carrier WCDMA Drive-up
VDD = 30 V, IDQ = 1.85 A, ƒ = 1842 MHz, 3GPP
WCDMA signal, PAR = 7.5 dB,
10 MHz carrier spacing
-30 35
-35
Efficiency
-40
30
25
IM3
-45
-50
ACPR
20
15
10
-55
38
40 42 44 46 48
Average Output Power (dBm)
5
50
Features
• Broadband internal input and output matching
• Enhanced for use in DPD error correction systems
• Typical two-carrier WCDMA performance,
1880 MHz, 30 V
- Average output power = 50 W
- Linear gain = 19 dB
- Drain efficiency = 28 %
- Intermodulation distortion = –35 dBc
• Typical CW performance, 1880 MHz, 30 V
- Output power at P1dB = 240 W
- Efficiency = 55%
• Increased negative gate-source voltage range for
improved performance in Doherty peaking amplifiers
• Integrated ESD protection. Human Body Model,
Class 2 (minimum)
• Capable of handling 10:1 VSWR @ 30 V, 240 W
(CW) output power
• Pb-free, RoHS compliant
RF Characteristics
Two-carrier WCDMA Specifications (tested in Infineon test fixture)
VDD = 30 V, IDQ = 1.85 A, POUT = 50 W average
ƒ1 = 1840 MHz, ƒ2 = 1845 MHz, 3GPP signal, channel bandwidth = 3.84 MHz , peak/average = 7.5 dB @ 0.01% CCDF
Characteristic
Gain
Drain Efficiency
Intermodulation Distortion
Symbol
Gps
hD
IMD
All published data at TCASE = 25°C unless otherwise indicated
ESD: Electrostatic discharge sensitive device—observe handling precautions!
Data Sheet
1 of 12
Min
18
27
Typ
19
28
–35
Max
–31
Unit
dB
%
dBc
Rev. 07.1, 2013-08-06

1 page




PTFB182503EL pdf
PTFB182503EL
PTFB182503FL
Reference Circuit
PTFB182503EL/FL_INPUT
C801
1000 pF
C802
1000 pF
R802
1200 Ohm
R801
1300 Ohm
S3
8
In
NC
4
2
1
Out
NC
3 6 75
C803
1000 pF
R803
100 Ohm
2C
14
BS
3E
S2
S1
R804
10 Ohm
R805
10 Ohm
3
TL112
RF_IN
TL115
TL108 2 3
1
TL124
R101
10 Ohm
TL116
TL132 2 3
1
C102
4710000 pF
TL121
TL110
12
3
TL118
C105
10 pF
TL125
TL107
TL117
TL113
TL102 TL111
TL127
C101
7.5 pF
TL104 TL131
TL133
TL129
12
3
TL130
TL128
PTFB182503EL/FL_OUTPUTTL114
TL139 2 3
C103
4710000 pF
C104
0.3 pF
1
TL103
TL105
2
13
4
TL122
TL138
TL137
TL136 2 3
1
TL123
R102
10 Ohm
C106
10 pF
TL119
TL120
TL109
3
21
TL101
TL126 TL106
b182503efl_bdin_08-17-2010
TL135
GATE DUT
(Pin G)
er = 3.48
H = 30 mil
RO/RO4350B1
TL134
Reference circuit input schematic for ƒ = 1880 MHz
C207
10000000 pF
DUT
(Pin V)
TL225 2 3
1
TL207
C210
100000 pF
TL228
3
21
C215
2200000 pF
TL218
3
21
C203
1000000 pF
TL217
3
21
TL210
TL211
12
3
C202
10000000 pF
TL214
VDD
C206
0.6 pF
C211
0.9 pF
TL220
DRAIN DUT
(Pin D)
TL237
TL226 TL204
TL241
TL239
2
13
4
TL240
TL208
TL238
C205
0.6 pF
TL236
TL233
TL231
TL230 TL232
2
13
4
TL234
C212
0.9 pF
TL229
TL223
C214
TL235 10 pF
TL205
TL221
TL202 TL222
DUT
(Pin V)
TL206
TL224
2
3
1
C208
10000000 pF
TL213
12
3
C209
100000 pF
TL227
12
3
C213
2200000 pF
TL212
12
3
C201
1000000 pF
C204
10000000 pF
TL209
TL216
3
b182503efl_bdout_08-17-2010
21
TL215
VDD
TL219
TL242
TL201 TL203
RF_OUT
er = 3.48
H = 30 mil
RO/RO4350B1
Reference circuit output schematic for ƒ = 1880 MHz
Data Sheet
5 of 12
Rev. 07.1, 2013-08-06

5 Page





PTFB182503EL arduino
PTFB182503EL
PTFB182503FL
Package Outline Specifications (cont.)
Package H-34288-4/2
45° X 2.032
[45° X .080]
2X 30°
V
22.860
[.900]
CL
D
2X 5.080
[.200]
2X 1.143
[.045]
V 4.889±.510
[.192±.020]
CL
4X
R0.508
+.381
-.127
[R.020+-.0.00155 ]
G
2X 12.700
[.500]
22.352±.200
[.880±.008]
9.398
[.370]
9.779
[.385]
19.558±.510
[.770±.020]
[ ]4..013599++--..10..2020517540
1.575
[.062] (SPH)
1.016
[.040]
CL
23.114
[.910]
H-34288-4/2_po_03_08-13-2012
S
Diagram Notes—unless otherwise specified:
1. Interpret dimensions and tolerances per ASME Y14.5M-1994.
2. Primary dimensions are mm. Alternate dimensions are inches.
3. All tolerances ±0.127 [0.005] unless specified otherwise.
4. Pins: D – drain; G – gate; S – source; V – VDD
5. Lead thickness: 0.10 + 0.051/–0.025 mm [0.004 + 0.002/–0.001 inch].
6. Gold plating thickness: 0.25 micron [10 microinch] max.
Find the latest and most complete information about products and packaging at the Infineon Internet page
http://www.infineon.com/rfpower
Data Sheet
11 of 12
Rev. 07.1, 2013-08-06

11 Page







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