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PDF ICS307-02 Data sheet ( Hoja de datos )
| Número de pieza | ICS307-02 | |
| Descripción | SERIALLY PROGRAMMABLE CLOCK SOURCE | |
| Fabricantes | IDT | |
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SERIALLY PROGRAMMABLE CLOCK SOURCE
DATASHEET
ICS307-01/-02
Description
The ICS307-01 and ICS307-02 are versatile serially
programmable clock sources which take up very little
board space. They can generate any frequency from 6
to 200 MHz and have a second configurable output.
The outputs can be reprogrammed on the fly and will
lock to a new frequency in 10 ms or less. Smooth
transitions (in which the clock duty cycle remains near
50%) are guaranteed if the output divider is not
changed.
The devices includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
The ICS307-02 features a default clock output at
start-up and is recommended for all new designs.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
skew, use the ICS527-01.
Features
• Packaged in 16-pin (150 mil wide) SOIC – Pb-free,
RoHS compliant
• Highly accurate frequency generation
• Serially programmable: user determines the output
frequency via a 3 wire interface
• Eliminates need for custom quartz
• Input crystal frequency of 5 - 27 MHz
• Output clock frequencies up to 200 MHz
• Power down tri-state mode
• Very low jitter
• Operating voltage of 3.3 V or 5 V
• 25 mA drive capability at TTL levels
• Industrial temperature version available
Block Diagram
SCLK
DATA
STROBE
X1/ICLK
Crystal or
clock input
X2
TTL
9 V8:V0
Shift
Register
2
3
2
7
C1:C0
S2:S0
F1:F0
R6:R7
Crystal
Oscillator
Reference
Divider
Optional crystal capacitors
VDD
VCO
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
GND
Output
Divider
3
S2:S0
Function
Select
3
F1:F0
CLK1
PDTS
CLK2
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
1
ICS307-01/-02 REV J 051310
1 page  
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Bypass Mode
If R6:0 is programmed to 0000000, the PLL is powered down and bypassed; the reference frequency will
come from both CLK1 and CLK2. It is possible to generate glitches going into and out of this mode.
Configuring the ICS307
The ICS307 can be programmed to set the output functions and frequencies. The three data bytes are
written in DATA pin in this order:
C1 C0 TTL F1 F0 S2 S1 S0 V8 V7 V6 V5 V4 V3 V2 V1 V0 R6 R5 R4 R3 R2 R1 R0
MSB
LSB MSB
LSB MSB
LSB
C1 is loaded into the port first and R0 last.
R6:R0 Reference Divder Word (RDW)
V8:V0 VCO Divider Word (VDW)
S2:S0 Output Divider Select (OD)
F1:F0 Function of CLK2 Output
TTL Duty Cycle Settings
C1:C0 Internal Load Capacitance for Crystal
The ICS307 can be reprogrammed at any time during operation. If R6:0, V8:0, TTL, or C1:0 are changed, the
frequency will transition smoothly to the new value over about 1 ms, without glitches or short cycles. If S2:0 is
changed, it is possible to generate glitches on CLK1 and also on CLK2 for F1:0 = 1 1.
Changing F1:0 will generate glitches on CLK2.
Power up default values for ICS307-02
00100011
00000100
The input frequency will come from both outputs.
00000110
A warning about using the default configuration with input frequencies lower than 13.75 MHz
The VCO will run only as low as its minimum frequency, which is guaranteed to be no more than 55 MHz.
So, in the powerup default condition, the PLL is guaranteed to lock to the input frequency down to 55/4 =
13.75 MHz. However, the part will typically run much slower. The typical minimum VCO frequency is about
30 - 40 MHz, depending on voltage, temperature, and lot variation; so in the powerup default setting, the
CLK2 output will be a minimum of 7.5 - 10 MHz even if the input frequency is lower than that. The output is
not locked to the reference input and so the frequency is not very stable and the phase noise is higher. In
this condition, the CLK2 output will accurately provide the reference frequency down to 0 Hz because this
signal path bypasses the PLL.
Power-down Mode
When the PDTS pin is pulled low, the chip will enter the power-down mode, where the output clocks are
tri-stated and the rest of the chip is powered down. The chip can be programmed during power-down
mode, however, if the chip is programmed during operation and enters power-down mode, the registers will
return to their settings and not reset when exiting power-down mode (PDTS pin is pulled high).
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
5
ICS307-01/-02 REV J 051310
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ICS307-02.PDF ] | |
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