RK3066 Datasheet PDF - Rockchip
| Part Number | RK3066 | |
| Description | High Performance Processor | |
| Manufacturers | Rockchip | |
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There is a preview and RK3066 download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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RK3066 Datasheet brief
Rev1.0
RK3066 Datasheet brief
Revision 1.0
Feb. 2012
Rockchips Confidential
1
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RK3066 Datasheet brief
Rev1.0
64KB internal SRAM for security and non-security access, detailed size is
programmable
2KB internal SRAM shared with NandC
External off-chip memory①
DDR3/LVDDR3, 16/32bits data width, 2 ranks, 2GB(max) address space per rank
LPDDR, 32bits data width, 2 ranks, 2GB(max) address space per rank
LPDDR2, 32bits data width, 2 ranks, 2GB(max) address space per rank
Async SRAM/Nor Flash, 8/16bits data width,2banks,1MB(max) address space per
bank
Async Nand Flash(include LBA Nand), 8/16bits data width, 8 banks
Sync DDR Nand Flash , 8bits data width, 8 banks
1.2.3 Internal Memory
Internal BootRom
Size : 10KB
Support system boot from the following device :
8bits/16bits Async Nand Flash
SPI0 interface
eMMC interface
Support system code download by the following interface:
USB OTG
UART0 in CPU system
Internal SRAM
Size : 64KB
Support security and non-security access
512KB internal SRAM shared with L2 Cache for Cortex-A9
1.2.4 External Memory or Storage device
Dynamic Memory Interface (DDR3/LVDDR3/LPDDR/LPDDR2)
Compatible with JEDEC standard DDR3/LVDDR3/LPDDR/LPDDR2 SDRAM
Support up to 2 ranks (chip selects), maximum 2GB address space per rank
16bits/32bits data width is software programmable
Programmable timing parameters support DDR3/LPDDR/LPDDR2 SDRAM from
various vendor
Low power modes, such as power-down and self-refresh for DDR3/LVDDR3/
LPDDR/LPDDR2 SDRAM; clock stop and deep power-down for LPDDR/LVDDR3/
LPDDR2 SDRAM
Compensation for board delays and variable latencies through programmable
pipelines
Programmable output and ODT impedance with dynamic PVT compensation
Support one low-power work mode: power down DDR PHY and most of DDR IO
except two CS and two CKE output signals, make SDRAM still in self-refresh state
to prevent data missing.
Static Memory Interface (ASRAM/Nor Flash)
Compatible with standard async SRAM or Nor Flash
Support up to 2 banks (chip selects), maximum 1MB address space per bank
For bank0, 8bits/16bits data width is software programmable; For bank1, 16bits
data width is fixed
Support separately data and address bus, also support shared data and address
bus to save IO numbers
Nand Flash Interface
Support 8bits/16bits async nand flash, up to 8 banks
Support 8bits sync DDR nand flash, up to 8 banks
Rockchips Confidential
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for RK3066 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ RK3066.PDF Datasheet ] | |
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