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PDF THCV218 Data sheet ( Hoja de datos )
| Número de pieza | THCV218 | |
| Descripción | HS High-speed video data receiver | |
| Fabricantes | THine Electronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de THCV218 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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THCV217-THCV218_Rev.2.20_E
THCV217 and THCV218
V-by-One® HS High-speed Video Data Transmitter and Receiver
General Description
THCV217 and THCV218 are designed to support
video data transmission between the host and display.
One high-speed lane can carry up to 32bit data and 3
bits of synchronizing signals at a pixel clock
frequency from 20MHz to 85MHz.
The chipset, which has two high-speed data lanes,
can transmit video data up to 1080p/10b/60Hz. The
maximum serial data rate is 3.4Gbps/lane.
Features
Color depth selectable: 24(8×3)/32(10×3)bit
Single-in/Single-out, Single-in/Dual-out, and
Dual-in/Dual-out selectable for THCV217
Single-in/Single-out, Dual-in/Single-out, and
Dual-in/Dual-out selectable for THCV218
AC coupling for high-speed lines
CORE 1.8V, CMOS IO 3.3V
Package: 217(TFBGA105), 218(TFBGA145)
Wide frequency range
CDR requires no external frequency reference
Spread Spectrum Clocking tolerant
Up to 30kHz / ±0.5% (center spread)
V-by-One® HS standard Version1.4 compliant.
Product
Link
Pixel Clock
Frequency
THCV217 Si/So 20MHz to 85MHz
Di/Do
Si/Do 40MHz to 170MHz
THCV218 Si/So 20MHz to 85MHz
Di/Do
Di/So 40MHz to 170MHz
Si/So: Single-in/Single-out, Di/Do: Dual-in/Dual-out
Di/So: Dual-in/Single-out, Si/Do: Single-in/Dual-out
Block Diagram
R1[9:0]
G1[9:0]
B1[9:0]
CONT1[2:1]
CMOS
R2[9:0]
G2[9:0]
B2[9:0]
CONT2[2:1]
HSYNC
VSYNC
DE
CLKIN
MODE
DEMUX
COL
BET
PRE
R/F
PDN
THCV217
Controls
TX0p
TX0n
RX0p
RX0n
CML
TX1p
TX1n
RX1p
RX1n
Open
Drain
HTPDN
LOCKN
HTPDN
LOCKN
DGLOCK
THCV218
Controls
R1[9:0]
G1[9:0]
B1[9:0]
CONT1[2:1]
CMOS
R2[9:0]
G2[9:0]
B2[9:0]
CONT2[2:1]
HSYNC
VSYNC
DE
CLKOUT
MODE1,0
COL
PLL
BET
R/F
DKEN,DK
PDN,OE
BETOUT
Copyright(C)2017 THine Electronics,Inc.
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THine Electronics, Inc.
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THCV217-THCV218_Rev.2.20_E
Pin Description
THCV217
THCV217 Pin Description
Name
Ball #
Type*
Description
TX0n,TX0p
E10,E11
CO CML output for Lane0
TX1n,TX1p
F10,F11
CO CML output for Lane1. Must be left OPEN when not used.
R19-R10
B8,A8,B9,A9,
B10,A10,B11,
A11,C10,C11
I3 1st pixel data inputs
G19-G10
B3,A3,B4,A4,
B5,A5,B6,
A6,B7,A7
I3 1st pixel data inputs
B19-B10
E2,E1,D2,D1,
C2,C1,B2,
B1,A2,A1
I3 1st pixel data inputs
CONT11,12
D10,D11
I3 User defined data inputs, serialized with 1st pixel data. Active only in 10bit mode.
R29-R20
K2,K1,J2,J1,
H2,H1,G2,
G1,F2,F1
I3 2nd pixel data inputs
G29-G20
K6,L6,K5,L5,
K4,L4,K3,
L3,L2,L1
I3 2nd pixel data inputs
B29-B20
H10,H11,K10,
L10,K9,L9,
K8,L8,K7,L7
I3 2nd pixel data inputs
CONT21,22
DE
G10,G11
J11
I3 User defined data inputs, serialized with 2nd pixel data. Active only in 10bit
I3 mDEodinep. ut
HSYNC
VSYNC
L11
K11
I3 Hsync input
I3 Vsync input
CLKIN J10 I3 Pixel clock input
HTPDN
C8
I3L
Hot plug detect input.
Must be connected to Rx HTPDN with a 10kW pull-up resistor.
LOCKN
C9
I3L
Lock detect input.
Must be connected to Rx LOCKN with a 10kW pull-up resistor.
*type symbol
CO=CML Output
I3=3.3V CMOS input, I3L=Low speed 3.3V CMOS input
O3=3.3V CMOS output
P=1.8V power supply, P3=3.3V power supply
Copyright(C)2017 THine Electronics,Inc.
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THCV217-THCV218_Rev.2.20_E
Operation Mode and Color Depth Mode function
THCV217 and 218 support a variety of operation modes to optimize power consumption, number of PCB
traces, or signal integrity. Refer to Table 2, Table 3, and Figure 3 for details.
COL
L
L
L
L
H
H
H
H
DEMUX
L
L
H
H
L
L
H
H
MODE
L
H
L
H
L
H
L
H
Description
10bit Dual-in/Dual-out
10bit Single-in/Single-out
10bit Single-in/Dual-out
Reserved (Forbidden)
CMOS Input
CLKIN Range
# of data
20 to 85 MHz
(32+3)×2
20 to 85 MHz
(32+3)×1
40 to 170 MHz
-
(32+3)×1
-
8bit Dual-in/Dual-out
8bit Single-in/Single-out
8bit Single-in/Dual-out
Reserved (Forbidden)
20 to 85 MHz
20 to 85 MHz
40 to 170 MHz
-
(24+3)×2
(24+3)×1
(24+3)×1
-
Table 2. THCV217 operation mode select
CML Output
TX0/1 Range
# of lanes
0.8 to 3.4Gbps
2
0.8 to 3.4Gbps
1
0.8 to 3.4Gbps
-
2
-
0.6 to 2.55Gbps
2
0.6 to 2.55Gbps
1
0.6 to 2.55Gbps
2
--
COL
L
L
L
L
H
H
H
H
MODE1
L
L
H
H
L
L
H
H
MODE0
L
H
L
H
Description
10bit Dual-in/Dual-out
10bit Dual-in/Single-out
10bit Single-in/Single-out
Reserved (Forbidden)
CML Input
RX0/1 Range
# of lanes
0.8 to 3.4Gbps
2
0.8 to 3.4Gbps
2
0.8 to 3.4Gbps
-
1
-
L 8bit Dual-in/Dual-out
H 8bit Dual-in/Single-out
L 8bit Single-in/Single-out
H Reserved (Forbidden)
0.6 to 2.55Gbps
0.6 to 2.55Gbps
0.6 to 2.55Gbps
-
2
2
1
-
Table 3. THCV218 operation mode select
CMOS Output
CLKOUT Range # of data
20 to 85 MHz
(32+3)×2
40 to 170 MHz
(32+3)×1
20 to 85 MHz
-
(32+3)×1
-
20 to 85 MHz
(24+3)×2
40 to 170 MHz
(24+3)×1
20 to 85 MHz
(24+3)×1
--
Copyright(C)2017 THine Electronics,Inc.
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet THCV218.PDF ] | |
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