PDF 21140A Data sheet ( Hoja de datos )

Número de pieza	21140A
Descripción	PCI Fast Ethernet LAN Controller
Fabricantes	Digital Equipment
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No Preview Available ! DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller Data Sheet Order Number: EC–QN7PF–TE Revision/Update Information: . Hardware Version: This is a revised document. It supersedes the DIGITAL Semiconductor 21140A PCI Fast Ethernet LAN Controller Data Sheet, EC–QN7PE–TE. This document describes the 21140–AD, the 21140–AE, and the 21140–AF. Digital Equipment Corporation Maynard, Massachusetts http://www.digital.com/semiconductor 1 page Contents 1 21140A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Signal Reference Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Pin Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Signal Grouping by Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical and Environmental Specifications . . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.7 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 3.8 3.8.1 3.8.2 3.9 3.10 3.11 3.11.1 3.11.2 Voltage Limit Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Limit Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Current and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI I/O Voltage Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial, MII/SYM, Boot ROM, Serial ROM, and General-Purpose Port Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Network Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial 10-Mb/s Timing—Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial 10-Mb/s Timing—Collision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial 10 Mb/s Timing—Receive, Start of Packet . . . . . . . . . . . . . . . . . . . . . Serial 10-Mb/s Timing—Receive, Start, and End of Packet . . . . . . . . . . . . . MII/SYM Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MII/SYM 10/100-Mb/s and 10-Mb/s Timing—Transmit . . . . . . . . . . . . . . . . . MII/SYM 10/100-Mb/s Timing—Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . MII/SYM 10/100-Mb/s Timing—Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . MII/SYM 10/100-Mb/s Timing—Receive Error. . . . . . . . . . . . . . . . . . . . . . . . MII/SYM 10/100-Mb/s Timing—Carrier Sense and Collision . . . . . . . . . . . . . Boot ROM Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot ROM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot ROM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial ROM Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Register Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Joint Test Action Group—Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Boundary-Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 3 6 8 18 20 22 22 22 23 23 23 24 25 26 27 28 28 29 30 31 32 32 34 35 36 36 37 37 38 39 40 41 41 41 iii 5 Page Microarchitecture • Supports PCI read multiple command • Supports early interrupts on transmit and receive for improved performance • Implements low-power management with two power-saving modes (sleep or snooze) • Supports both PCI 5.0-V and 3.3-V signaling environments • Supports either big or little endian byte ordering for buffers and descriptors • Contains 8-bit, general-purpose, programmable register and corresponding I/O pins • Provides LED support for various network activity indications • Provides MicroWire interface for serial ROM (1K and 4K EEPROM) • Provides an upgradable boot ROM interface of up to 256KB • Supports automatic loading of subsystem vendor ID and subsystem ID from serial ROM to configuration register • Implements JTAG-compatible test-access port with boundary-scan pins • Supports IEEE 802.3, ANSI 8802-3, and Ethernet standards • Implements low-power, 3.3-V complementary metal-oxide semiconductor (CMOS) process technology • Supports PCI write and invalidate, and read line commands 1.3 Microarchitecture The following list describes the 21140A hardware components, and Figure 1 shows a block diagram of the 21140A: • PCI interface—Includes all interface functions to the PCI bus; handles all interconnect control signals; and executes PCI DMA and I/O transactions. • DMA—Contains dual receive and transmit controller; handles data transfers between CPU memory and onchip memory. • FIFOs—Contains two FIFOs for receive and transmit; supports automatic packet deletion on receive (runt packets or after a collision) and packet retransmission after a collision on transmit. • TxM—Handles all CSMA/CD MAC1 transmit operations, and transfers data from transmit FIFO to the ENDEC for transmission. 21140A Overview 3 11 Page

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