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PDF SST26WF080BA Data sheet ( Hoja de datos )
| Número de pieza | SST26WF080BA | |
| Descripción | 1.8V 4 Mbit and 8 Mbit Serial Quad I/O (SQI) Flash Memory | |
| Fabricantes | Microchip | |
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SST26WF040B/040BA
SST26WF080B/080BA
1.8V 4 Mbit and 8 Mbit Serial Quad I/O (SQI) Flash Memory
Features
• Single Voltage Read and Write Operations
- 1.65-1.95V
• Serial Interface Architecture
- Mode 0 and Mode 3
- Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
• High Speed Clock Frequency
- 104 MHz max
• Burst Modes
- Continuous linear burst
- 8/16/32/64 Byte linear burst with wrap-around
• Superior Reliability
- Endurance: 100,000 Cycles (min)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby current: 10 μA (typical)
- Deep Power-Down current: 1.8 μA (typical)
• Fast Erase Time
- Sector/Block Erase: 18 ms (typ), 25 ms (max)
- Chip Erase: 35 ms (typ), 50 ms (max)
• Page-Program
- 256 Bytes per page in x1 or x4 mode
• End-of-Write Detection
- Software polling the BUSY bit in status register
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Four 8 KByte top and bottom parameter overlay
blocks
- One 32 KByte top and bottom overlay block
- Uniform 64 KByte overlay blocks
• Write-Suspend
- Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Software Write Protection
- Individual-Block Write Protection with permanent
lock-down capability
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
- Read Protection on top and bottom 8 KByte
parameter blocks
• Security ID
- One-Time Programmable (OTP) 2 KByte,
Secure ID
- 64 bit unique, factory pre-programmed identifier
- User-programmable area
• Temperature Range
- Industrial: -40°C to +85°C
• Packages Available
- 8-contact WDFN (6mm x 5mm)
- 8-lead SOIC (150 mil)
- 8-contact USON (2mm x 3mm)
- 8-ball XFBGA (Z-Scale™)
• All devices are RoHS compliant
Product Description
The Serial Quad I/O™ (SQI™) family of flash-memory
devices features a six-wire, 4-bit I/O interface that allows for
low-power, high-performance operation in a low pin-count
package. SST26WF040B/040BA and SST26WF080B/
080BA also support full command-set compatibility to tradi-
tional Serial Peripheral Interface (SPI) protocol. System
designs using SQI flash devices occupy less board space
and ultimately lower system costs.
All members of the 26 Series, SQI family are manufactured
with proprietary, high-performance CMOS SuperFlash®
technology. The split-gate cell design and thick-oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches.
The SST26WF040B/040BA and SST26WF080B/
080BA significantly improves performance and reliabil-
ity, while lowering power consumption. This device
writes (Program or Erase) with a single power supply of
1.65-1.95V. The total energy consumed is a function of
the applied voltage, current, and time of application.
Since for any given voltage range, the SuperFlash
technology uses less current to program and has a
shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash memory technologies.
SST26WF040B/040BA and SST26WF080B/080BA is
offered in 8-contact WDFN (6 mm x 5 mm), 8-lead SOIC
(150 mil), 8-contact USON, and 8-ball XFBGA (Z-Scale™)
packages. See Figure 2-1 for pin assignments.
Two configurations are available upon order:
SST26WF040B and SST26WF080B default at power-
up has the WP# and Hold# pins enabled and
SST26WF040BA and SST26WF080BA default at
power-up has the WP# and Hold# pins disabled.
2014 Microchip Technology Inc.
DS20005283B-page 1
1 page  
SST26WF040B/040BA SST26WF080B/080BA
TABLE 2-1:
Symbol
SCK
SIO[3:0]
SI
SO
CE#
WP#
HOLD#
VDD
VSS
PIN DESCRIPTION
Pin Name
Serial Clock
Serial Data
Input/Output
Serial Data Input
for SPI mode
Serial Data Output
for SPI mode
Chip Enable
Write Protect
Hold
Power Supply
Ground
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device or data out of
the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
To transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a
power on reset.
To transfer data serially out of the device. Data is shifted out on the falling edge
of the serial clock. SO is the default state after a power on reset.
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.
The WP# pin is used in conjunction with the WPEN and IOC bits in the configu-
ration register to prohibit Write operations to the Block-Protection register. This
pin only works in SPI, single-bit and dual-bit Read mode.
Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read
mode. This pin must be tied high when not in use.
To provide power supply voltage.
2014 Microchip Technology Inc.
DS20005283B-page 5
5 Page 
SST26WF040B/040BA SST26WF080B/080BA
4.5.3
WRITE SUSPEND PROGRAM
STATUS (WSP)
The Write Suspend-Program status (WSP) bit indi-
cates when a Program operation has been suspended.
The WSP is ‘1’ after the host issues a suspend com-
mand during the Program operation. Once the sus-
pended Program resumes, the WSP bit is reset to ‘0’.
4.5.4
WRITE PROTECTION LOCK-DOWN
STATUS (WPLD)
The Write Protection Lock-Down status (WPLD) bit
indicates when the Block-Protection register is locked-
down to prevent changes to the protection settings.
The WPLD is ‘1’ after the host issues a Lock-Down
Block-Protection command. After a power cycle, the
WPLD bit is reset to ‘0’.
4.5.5 SECURITY ID STATUS (SEC)
The Security ID Status (SEC) bit indicates when the
Security ID space is locked to prevent a Write com-
mand. The SEC is ‘1’ after the host issues a Lockout
SID command. Once the host issues a Lockout SID
command, the SEC bit can never be reset to ‘0.’
4.5.6 BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. If the BUSY
bit is ‘1’, the device is busy with an internal Erase or
Program operation. If the bit is ‘0’, no Erase or Program
operation is in progress.
4.5.7 CONFIGURATION REGISTER
The Configuration register is a Read/Write register that
stores a variety of configuration information. See Table
4-3 for the function of each bit in the register.
TABLE 4-3: CONFIGURATION REGISTER
Bit Name
0 RES
1 IOC
2 RES
3 BPNV
4 RES
5 RES
6 RES
7 WPEN
Function
Default at Power-up
Reserved
0
I/O Configuration for SPI Mode
1 = WP# and HOLD# pins disabled
0 = WP# and HOLD# pins enabled
01
Reserved
0
Block-Protection Volatility State
1 = No memory block has been permanently locked
0 = Any block has been permanently locked
1
Reserved
0
Reserved
0
Reserved
0
Write-Protection Pin (WP#) Enable
1 = WP# enabled
0 = WP# disabled
02
Read/Write (R/W)
R
R/W
R
R
R
R
R
R/W
1. SST26WF040B and SST26WF080B default at Power-up is ‘0’
SST26WF040BA and SST26WF080BA default at Power-up is ‘1’
2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down.
2014 Microchip Technology Inc.
DS20005283B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST26WF080BA.PDF ] | |
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