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PDF RTL8169SC-GR Data sheet ( Hoja de datos )
| Número de pieza | RTL8169SC-GR | |
| Descripción | INTEGRATED GIGABIT ETHERNET CONTROLLER | |
| Fabricantes | Realtek Semiconductor | |
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RTL8169SC
RTL8169SC-GR
INTEGRATED GIGABIT ETHERNET CONTROLLER
(NIC) (MiniPCI)
DATASHEET
Rev. 1.2
22 December 2005
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-557-6047
www.realtek.com.tw
1 page  
RTL8169SC
Datasheet
List of Tables
TABLE 1. POWER MANAGEMENT/ISOLATION ...............................................................................................................................4
TABLE 2. PCI INTERFACE.............................................................................................................................................................5
TABLE 3. EEPROM .....................................................................................................................................................................7
TABLE 4. TRANSCEIVER INTERFACE ............................................................................................................................................7
TABLE 5. CLOCK ..........................................................................................................................................................................8
TABLE 6. REGULATOR & REFERENCE ..........................................................................................................................................8
TABLE 7. LEDS............................................................................................................................................................................8
TABLE 8. POWER & GROUND .......................................................................................................................................................9
TABLE 9. NC (NOT CONNECTED) PINS.........................................................................................................................................9
TABLE 10. EEPROM INTERFACE ................................................................................................................................................22
TABLE 11. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................26
TABLE 12. RECOMMENDED OPERATING CONDITIONS .................................................................................................................26
TABLE 13. CRYSTAL REQUIREMENTS..........................................................................................................................................26
TABLE 14. THERMAL CHARACTERISTICS.....................................................................................................................................27
TABLE 15. DC CHARACTERISTICS...............................................................................................................................................27
TABLE 16. EEPROM ACCESS TIMING PARAMETERS ..................................................................................................................28
TABLE 17. PCI BUS TIMING PARAMETERS ..................................................................................................................................29
TABLE 18. MEASUREMENT CONDITION PARAMETERS.................................................................................................................30
TABLE 19. CLOCK AND RESET SPECIFICATIONS ..........................................................................................................................31
TABLE 20. ORDERING INFORMATION ..........................................................................................................................................41
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) v
Track ID: JATR-1076-21 Rev. 1.2
5 Page 
RTL8169SC
Datasheet
5.2. PCI Interface
Symbol
PCIADPIN31-0
CBEBPIN7-4
CBEBPIN3-0
PCICLK
DEVSELB
FRAMEB
GNTB
REQB
IDSEL
INTAB
Table 2. PCI Interface
Type
Pin No Description
T/S 33, 34, 36, AD31-0: Low 32-bit PCI address and data multiplexed pins. The address
37, 39, 40, phase is the first clock cycle in which FRAMEB is asserted. During the
42, 43, 47, address phase, AD31-0 contains a physical address (32 bits). For I/O, this is
49, 50, 53, a byte address, and for configuration and memory, it is a double-word
55, 57, 58, address. The RTL8169SC supports both big-endian and little-endian byte
59, 79, 82, ordering. Write data is stable and valid when IRDYB is asserted. Read data
83, 85, 86, is stable and valid when TRDYB is asserted. Data I is transferred during
87, 89, 90, those clocks where both IRDYB and TRDYB are asserted.
93, 95, 96, PCIADPIN31-24 are shared with Boot ROM data pins, while
97, 98, 102, PCIADPIN16-0 are shared with Boot ROM address pins.
103, 104
T/S PCI bus command and Byte Enables multiplex pins. During the address
phase of a transaction, CBEBPIN7-4 defines the bus command. During the
data phase, CBEBPIN7-4 are used as Byte Enables. The Byte Enables are
valid for the entire data phase and determine which byte lanes carry
meaningful data. CBEBPIN4 applies to byte 4, and CBEBPIN7 applies to
byte 7.
T/S 44, 60, 77, 92 PCI bus command and Byte Enables multiplex pins. During the address
phase of a transaction, CBEBPIN3-0 defines the bus command. During the
data phase, CBEBPIN3-0 are used as Byte Enables. The Byte Enables are
valid for the entire data phase and determine which byte lanes carry
meaningful data. CBEBPIN0 applies to byte 0, and CBEBPIN3 applies to
byte 3.
I 28 PCI clock: This clock input provides timing for all PCI transactions and is
input to the PCI device. Supports up to a 66MHz PCI clock.
S/T/S
68 Device Select: As a bus master, the RTL8169SC samples this signal to
insure that a PCI target recognizes the destination address for the data
transfer. As a target, the RTL8169SC asserts this signal low when it
recognizes its target address after FRAMEB is asserted.
S/T/S
61 Cycle Frame: As a bus master, this pin indicates the beginning and duration
of an access. FRAMEB is asserted low to indicate the start of a bus
transaction. While FRAMEB is asserted, data transfer continues. When
FRAMEB is de-asserted, the transaction is in the final data phase.
As a target, the device monitors this signal before decoding the address to
check if the current transaction is addressed to it.
I 29 Grant: This signal is asserted low to indicate to the RTL8169SC that the
central arbiter has granted the ownership of the bus to the RTL8169SC. This
input is used when the device is acting as a bus master.
T/S 30 Request: The RTL8169SC will assert this signal low to request the
ownership of the bus from the central arbiter.
I 46 Initialization Device Select: This pin allows the device to identify when
configuration read/write transactions are intended for it.
O/D 25 Interrupt A: Used to request an interrupt. It is asserted low when an
interrupt condition occurs, as defined by the Interrupt Status, Interrupt
Mask.
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI)
5
Track ID: JATR-1076-21 Rev. 1.2
11 Page | ||
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