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25Q80BSIG Datasheet PDF - GigaDevice

Part Number 25Q80BSIG
Description Dual and Quad Serial Flash
Manufacturers GigaDevice 
Logo GigaDevice Logo 

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25Q80BSIG datasheet, circuit
25Q80BSIG
FEATURES
8M-bit Serial Flash
-1024K-byte
-256 bytes per programmable page
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 180Mbits/s
-Quad I/O Data transfer up to 360Mbits/s
Program/Erase Speed
-Page Program time: 0.7ms typical
-Sector Erase time: 100ms typical
-Block Erase time: 0.3/0.4/0.8s typical
-Chip Erase time: 8s typical
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64/128K-byte
Low Power Consumption
-20mA maximum active current
-5uA maximum power down current
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top or Bottom, Sector or Block selection
Minimum 100,000 Program/Erase Cycles
Note: 1.Please contact Gigadevice for details
Advanced security Features(1)
-16-Bit Customer ID
-Security Architecture
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
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GENERAL DESCRIPTION
The GD25Q80 (8M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 180Mbits/s and the Quad I/O & Quad output data is transferred with speed of
360Mbits/s.
CONNECTION DIAGRAM
CS# 1
8
SO
WP#
27
Top View
36
VSS
45
8LEAD SOP/DIP
VCC
HOLD#
SCLK
SI
1
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25Q80BSIG equivalent
Uniform Sector
Dual and Quad Serial Flash
GD25Q80
Data Protection
The GD25Q80 provide the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE)
-Block Erase (BE)
-Chip Erase (CE)
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory
array that can be read but not change.
Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
Table1. GD25Q80 Protected area size
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0
XX0 0 0
Blocks
NONE
Addresses
NONE
Density
NONE
Portion
NONE
00001
15
0F0000H-0FFFFFH
64KB
Upper 1/16
0 0 0 1 0 14 to 15
0E0000H-0FFFFFHhttp://www.DataSheet4U.net/
128KB
Upper 1/8
0 0 0 1 1 12 to 15
0C0000H-0FFFFFH
256KB
Upper 1/4
0 0 1 0 0 8 to 15
080000H-0FFFFFH
512KB
Upper 1/2
01001
0
000000H-00FFFFH
64KB
Lower 1/16
01010
0 to 1
000000H-01FFFFH
128KB
Lower 1/8
01011
0 to 3
000000H-03FFFFH
256KB
Lower 1/4
01100
0 to 7
000000H-07FFFFH
512KB
Lower 1/2
0 X 1 0 1 0 to 15
000000H-0FFFFFH
1M
ALL
X X 1 1 X 0 to 15
000000H-0FFFFFH
1M
ALL
10001
15
0FF000H-0FFFFFH
4KB Top Block
10010
15
0FE000H-0FFFFFH
8KB Top Block
10011
15
0FC000H-0FFFFFH
16KB
Top Block
1010X
15
0F8000H-0FFFFFH
32KB
Top Block
11001
0
000000H-000FFFH
4KB Bottom Block
11010
0
000000H-001FFFH
8KB Bottom Block
11011
0
000000H-003FFFH
16KB
Bottom Block
1110X
0
000000H-007FFFH
32KB
Bottom Block
5
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Information Total 30 Pages
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