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PDF HA-5320-883 Data sheet ( Hoja de datos )

Número de pieza HA-5320-883
Descripción High Speed Precision Sample and Hold Amplifier
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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TM HA-5320/883
April 2002
High Speed Precision Sample and Hold Amplifier
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Gain, DC . . . . . . . . . . . . . . . . . . . . . . . . 2 x 106 V/V (Typ)
• Acquisition Time . . . . . . . . . . . . . . . 1.0µs (0.01%) (Typ)
• Droop Rate . . . . . . . . . . . . . . . . 0.08µV/µs (+25oC) (Typ)
17µV/µs (Full Temperature) (Typ)
• Aperture Time . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Typ)
• Hold Step Error . . . . . . . . . . . . . . . . . . . . . . 1.0mV (Typ)
• Internal Hold Capacitor
• Fully Differential Input
• TTL Compatible
Applications
• High Bandwidth Precision Data Acquisition Systems
• Inertial Navigation and Guidance Systems
• Ultrasonics
• SONAR / RADAR
• Digital to Analog Converter Deglitcher
Description
The HA-5320/883 was designed for use in precision, high speed
data acquisition systems.
The circuit consists of an input transconductance amplifier
capable of providing large amounts of charging current, a low
leakage analog switch, and an output integrating amplifier. The
analog switch sees virtual ground as its load; therefore, charge
injection on the hold capacitor is constant over the entire input/
output voltage range. The pedestal voltage resulting from this
charge injection can be adjusted to zero by use of the offset
adjust inputs. The device includes a hold capacitor. However, if
improved droop rate is required at the expense of acquisition
time, additional hold capacitance may be added externally.
This monolithic device is manufactured using the Intersil
Dielectric Isolation Process, minimizing stray capacitance and
eliminating SCR’s. This allows higher speed and latch-free
operation. For further information, please see Application Note
AN538.
Pinout
HA-5320/883 (CERDIP)
TOP VIEW
-INPUT 1
14 S/H CONTROL
+INPUT 2
13 SUPPLY GND
OFFSET ADJ 3
12 NC
OFFSET ADJ 4
V- 5
SIG GND 6
11 CEXT
10 NC
9 V+
OUTPUT 7
8 INT. BW
Ordering Information
PART NUMBER
HA1-5320/883
TEMPERATURE
RANGE
-55oC to +125oC
PACKAGE
14 Lead CerDIP
Functional Diagram
OFFSET
ADJUST
34
V+
9
-INPUT 1
+INPUT 2
HA-5320/883
100pF
-
+
7
OUTPUT
S/H
CONTROL
14
13
SUPPLY
GND
56
V- SIG
GND
11
CEXT
8
INTEGRATOR
BANDWIDTH
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
Spec Number 511096-883
FN2927.4

1 page




HA-5320-883 pdf
HA-5320/883
Die Characteristics
DIE DIMENSIONS:
92 x 152 x 19 ± 1mils
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16kÅ ± 2kÅ
GLASSIVATION:
TSyilpoxe:TNhiitcrkidnee(sSs:i31N24k)Åov±er2kSÅilox (SiO2, 5% Phos)
Nitride Thickness: 3.5kÅ ± 1.5kÅ
WORST CASE CURRENT DENSITY:
1.742 x 105 A/cm2
TRANSISTOR COUNT: 184
SUBSTRATE POTENTIAL: V-
Metallization Mask Layout
HA-5320/883
SUPPLY GND
(13)
CEXT
(11)
V+
(9)
S/H CTRL (14)
-INPUT (1)
+INPUT (2)
(3)
VIO ADJ
(4)
VIO ADJ
(5)
V-
(8) INT BW
(7) OUTPUT
(6) SIG GND
Spec Number 511096-883
5

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HA-5320-883 arduino
HA-5320/883
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as applica-
tion and design information only. No guarantee is implied.
Glossary of Terms
Acquisition Time
The time required following a “sample” command, for the
output to reach its final value within ±0.1% or ±0.01%. This is
the minimum sample time required to obtain a given accu-
racy, and includes switch delay time, slewing time and set-
tling time.
Charge Transfer
The small charge transferred to the holding capacitor from
the inter-electrode capacitance of the switch when the unit is
switched to the HOLD mode. Charge transfer is directly pro-
portional to sample-to-hold offset pedestal error, where:
Charge Transfer (pC) = CH (pF) x Offset Error (V)
Aperture Time
The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is the interval
between the conditions of 10% open and 90% open.
Hold Step Error
Hold Step Error is the output error due to Charge Transfer
(see above). It may be calculated from Charge Transfer,
using the following relationship:
HOLD STEP (V) =
CHARGE TRANSFER (pC)
HOLD CAPACITANCE (pF)
See Performance Curves.
Effective Aperture Delay Time (EADT)
The difference between propagation time from the analog
input to S/H switch, and digital delay time between the Hold
command and opening of the switch.
EADT may be positive, negative or zero. If zero, the S/H
amplifier will output a voltage equal to VIN at the instant the
Hold command was received. For negative EADT, the output
in Hold (exclusive of pedestal and droop errors) will
correspond to a value of VIN that occurred before the Hold
command.
Aperture Uncertainty
The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay
Uncertainty, Aperture Time Jitter, etc.) sets a limit on the
accuracy with which a waveform can be reconstructed from
sample data.
Drift Current
The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:
ID (pA) = CH (pF) x
V (V/s)
T
PARAMETER
Input Voltage Range
Offset Voltage Drift
Gain Bandwidth Product (CH = 100pF)
Gain Bandwidth Product (CH = 1000pF)
Full Power Bandwidth
Output Resistance (Hold Mode)
0.1% Acquisition Time
0.01% Acquisition Time
Effective Aperture Delay Time
Aperture Uncertainty
0.01% Hold Mode Settling Time
TYPICAL PERFORMANCE CHARACTERISTICS
CONDITIONS
Av = +1, VO = 200mVP-P, RL = 2K, CL = 50pF
Av = +1, VO = 200mVP-P, RL = 2K, CL = 50pF
VO = 20VP-P, RL = 2K, CL = 50pF
VO = 10V Step, RL = 2K, CL = 50pF
VO = 10V Step, RL = 2K, CL = 50pF
TEMPERATURE
Full
Full
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
TYP
±10
5
2
0.18
600
1.0
0.8
1.0
-25
0.3
165
UNITS
V
µV/oC
MHz
MHz
kHz
µs
µs
ns
ns
ns
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 511096-883
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