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PDF AS7C33128NTD32A Data sheet ( Hoja de datos )
| Número de pieza | AS7C33128NTD32A | |
| Descripción | 3.3V 128K X 32/36 SRAM | |
| Fabricantes | Alliance Semiconductor | |
| Logotipo |  |
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December 2002
AS7C33128NTD32A
AS7C33128NTD36A
9 .î 65$0 ZLWK 17'TM
Features
• Organization: 131,072 words × 32 or 36 bits NTD™1
architecture for efficient bus operation
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/4.0/5.0 ns
• Fast OE access time: 3.5/4.0/5.0 ns
• Fully synchronous operation
• Flow-through or pipelined mode
• Asynchronous output enable control
1. NTD™ is a trademark of Alliance Semiconductor Corporation.
Logic block diagram
• Economical 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Pin arrangement for TQFP (top view)
A[16:0]
17
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
FT
LBO
ZZ
DQ [a:d]
32/36
D AredgdirsetessrQ
Burst logic
CLK
Control
logic
CLK
D
Data
Input
Q
Register
CLK
CLK
CEN
17
17
17
DQ
Write delay
addr. registers
CLK
17
CLK
32/36
128K x 32/36
SRAM
Array
32/36
32/36
32/36
CLK
Output
OE Register
32/36
OE DQ [a:d]
DQPc, NC
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
FT
VDD
VDD
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd, NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14x20mm
80 DQPb, NC
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 VDD
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 DQPa, NC
Note: Pins 1,30,51,80 are NC for ×32
Selection Guide
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-166
6
166
3.5
475
130
30
-133
7.5
133
4
425
100
30
-100
10
100
5
325
90
30
Units
ns
MHz
ns
mA
mA
mA
Y
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1 page  
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Recommended operating conditions
Parameter
Supply voltage
3.3V I/O supply
voltage
2.5V I/O supply
voltage
Input voltages1
Address and
control pins
I/O pins
Ambient operating temperature
Symbol
VDD
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VIH
VIL
VIH
VIL
TA
Min
3.135
0.0
3.135
0.0
2.35
0.0
2.0
–0.52
2.0
-0.52
0
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V operation, contact factory for input specifications.
2 VIL min. = –2.0V for pulse width less than 0.2 x tRC.
Nominal
3.3
0.0
3.3
0.0
2.5
0.0
–
–
–
–
–
Max
3.465
0.0
3.465
0.0
2.65
0.0
VDD + 0.3
0.8
VDDQ + 0.3
0.8
70
Unit
V
V
V
V
V
V
V
°C
DC electrical characteristics for 3.3V I/O operation
166
Parameter
Input leakage current1
Output leakage
current
Sym Test conditions
| ILI | VDD = Max, Vin = VSS to VDD
| ILO |
OE ≥ VIH, VDD = Max,
Vout = VSS to VDD
Operating power supply
current
ICC
ISB
Standby power supply
current
ISB1
ISB2
Output voltage
VOL
VOH
CE = VIL, CE = VIH, CE = VIL,
f = fmax, Iout = 0 mA
Deselected, f = fmax
Deselected, f = 0,
all VIN ≤ 0.2V or ≥ VDD - 0.2V
Deselected, f=fMax, ZZ ≥ VDD -
0.2V All VIN ≤ VIL or ≥ VIH
IOL = 8 mA, VDDQ = 3.6V
IOH = –4 mA, VDDQ = 3.0V
Min
–
–
–
–
–
–
–
2.4
Max
2
2
475
130
30
30
0.4
–
1 LBO pin has an internal pull-up, and input leakage = ±10 µA.
Note: ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
133
Min Max
–2
–2
– 425
– 100
– 30
– 30
– 0.4
2.4 –
100
Min Max
–2
Unit
µA
– 2 µA
– 325 mA
– 90 mA
– 30 mA
– 30 mA
– 0.4 V
2.4 – V
Y
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5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet AS7C33128NTD32A.PDF ] | |
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