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PDF MB86606 Data sheet ( Hoja de datos )
| Número de pieza | MB86606 | |
| Descripción | Wide Fast-20 SCSI Protocol Controller | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-22420-1E
ASSP Communication Control
CMOS
Wide Fast-20 SCSI Protocol Controller
With PCI Interface
MB86606
s DESCRIPTION
The MB86606 is an intelligent SCSI Protocol Controller (SPC) which complies with ANSI (FAST-20) standard
and integrates a PCI local bus interface function. The specification of SCSI controller block is based on the
MB86605’s one which is a Wide SCSI-2 protocol controller, with addition of some enhancements such as
Fast-20 (ultra-SCSI) support and larger "Data Register FIFO" (512 bytes). The MB86606 is capable of
transfering data up to 40 Mbyte/sec. As for the SCSI bus pins, a totem pole type single-ended driver/receiver
is incorporated in the device so that it can drive the SCSI bus directly. Furthermore, the MB86606 is capable of
connecting the external differential type driver/receiver.
The SCSI bus sequence is controlled by commands issued via the system interface. So, it supports sequential
commands that perform the phase-to-phase sequences to reduce the overhead of system’s sequence
operations.
As another key feature to reduce the system overhead, the device has a 2 Kbytes user program memory to
store the user program with the commands. Due to this, all the SCSI bus sequences including the data transfer
can be performed automatically.
As the system interface block, it incorporates a 32-bit PCI local bus interface which makes MB86606 an Ideal
"on-board PCI-SCSI controller" as well as Host/RAID controllers for PCs, servers and work stations. It also
supports 16-bit separate MPU and DMA buses. For the on-chip PCI bus interface, the MB86606 also incorporates
a 32-bit DMA controller that is capable of supporting the scatter-gather function so that the data transfers can
be controlled by both user program and the host system.
The device is fabricated by the advanced CMOS process and is housed in an 144-pin plastic Low Profile Shrink
Quad Flat Package (Suffix: -PMT).
s PACKAGE
144 Pin, Plastic LQFP
1 page  
• PCI Bus Interface Mode
(TOP VIEW)
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C/BE2
FRAME
IRDY
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TRDY
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DEVSEL
STOP
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PERR
PAR
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5
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INDEX
(FPT-144P-M08)
MB86606
LDBOEP
V DD
DB12
105 DB13
DB14
DB15
V SS
UDBP
100 DB0
DB1
V SS
DB2
DB3
95 DB4
DB5
V SS
DB6
DB7
90 LDBP
ATN
V SS
BSY
ACK
85 RST
MSG
SEL
V SS
C/D
80 REQ
I/O
DB8
V SS
DB9
75 DB10
DB11
V DD
5
5 Page 
MB86606
3. 16-Bit Bus Mode – DMA Interface
Pin no.
Pin name I/O
Function
130 DREQ
This is used to output DMA transfer request signals to the
O
DMAC.
DMA data transfer between the SPC and memory is
requested.
129 DACK
This is used to input DMA-enabling signals from the DMAC.
I When the DMA enabling signal is active, DMA reading and
writing are executed.
138, 139, 141 to 144, 1, 3 DMD15 to 8
136 UDMDP
Upper byte and parity of DMA data bus
When CS1 input valid: The MPU data bus is directly
I/O connected.
When 80-series mode: The 2nd data is input/output.
When 68-series mode: The 1st data is input/output.
4, 5, 7, 9 to 11, 13, 14 DMD7 to 0
15 LDMDP
Lower byte and parity of DMA data bus
When CS1 input valid: The MPU data bus is directly
I/O connected.
When 80-series mode: The 1st data is input/output.
When 68-series mode: The 2nd data is input/output.
In 80-series mode: This is used to input the IORD or RD
signal for outputting data from the SPC
135
DMRD (DMR/W)
I
to the DMA bus.
In 68-series mode: This is used to input the R/W control
signal for outputting and inputting data
from the DMAC to the SPC.
In 80-series mode: This is used to input the IOWR or WR
signal for inputting data from the DMA
133
DMWR (DMLDS)
I
bus to the SPC.
In 68-series mode: This is used to input the LDS signal
output by the DMAC when the lower
byte of the DMA data bus is valid.
In 80-series mode: This is used to input the BHE signal
output by the DMAC when the upper
132
DMBHE (DMUDS)
I
byte of the DMA data bus is valid.
In 68-series mode: This is used to input the UDS signal
output by the DMAC when the upper
byte of the DMA data bus is valid.
125 DMA0
This is used to input the address data A0 signal output by
I the DMAC in the 80-series mode.
In 68-series mode: Connect to power supply pin (VDD).
This is used to input DMA-transfer-enabling signals.
TP When the TP signal is active, the SPC performs the DMA
126
(Transfer
I transfer.
permission)
When this signal becomes inactive during DMA transfer, the
transfer stops temporarily at the block boundary.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB86606.PDF ] | |
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