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PDF AA121XH03 Data sheet ( Hoja de datos )
| Número de pieza | AA121XH03 | |
| Descripción | XGA Color TFT LCD | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AA121XH03 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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1 page  
2. OVERVIEW
AA121XH03 is 12.1” color TFT-LCD (Thin Film Transistor Liquid Crystal Display) module
composed of LCD panel, driver ICs, control circuit, and backlight unit.
By applying 6 bit or 8 bit digital data, 1024 × 768, 262k-color or 16.7M-color images are displayed
on the 12.1” diagonal screen. Input power voltage is single 3.3V for LCD driving.
The type of data and control signals are digital and transmitted via LVDS interface per Typ. 65
MHz clock cycle.
Inverter for backlight is not included in this module. General specifications are summarized in the
following table:
ITEM
Display Area (mm)
Number of Dots
Pixel Pitch (mm)
Color Pixel Arrangement
Display Mode
Number of Color
Luminance (cd/m2)
Wide Viewing Angle Technology
Viewing Angle (CR ≥ 10)
Surface Treatment
Electrical Interface
Optimum Viewing Angle(Contrast ratio)
Module Size (mm)
Module Mass (g)
Backlight Unit
SPECIFICATION
245.76(H) × 184.32(V)
(12.106-inch diagonal)
1024 × 3 (H) × 768 (V)
0.240 (H) × 0.240 (V)
RGB vertical stripe
Normally white TN
262 k(6 bit/color), 16.7 M(8 bit/color)
320
Optical Compensation Film
-65~65° (H) -75~45° (V)
Anti-glare and hard-coating 3H
LVDS
6 o’clock
280.0 (W) × 210.0 (H) × 12.0 (D)
720
CCFL, 2-tubes, edge-light, replaceable
Characteristic value without any note is typical value.
MITSUBISHI Confidential
(4/27)
AA121XH03_02_05_First
5 Page 
6. INTERFACE TIMING
LVDS transmitter input signal
(1) Timing Specifications
ITEM
SYMBOL MIN.
TYP.
MAX.
UNIT
Frequency
DCLK Period
fCLK
50
65
80 MHz
tCLK
12.5
15.4
20
ns
Active Time
tHA 1024 1024 1024
tCLK
Horizontal Blanking Time
tHB
20
320 511 tCLK
Frequency
fH 42.4 48.4 60 kHz
DENA
Period
tH 16.6 20.7 23.6
Active Time tVA 768 768 768
μs
tH
Vertical Blanking Time
tVB
3
38
--
tH
Frequency
fV 55 60 75 Hz
Period
tV 13.3 16.7 18.2 ms
[Note]
1) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
2) DCLK should appear during all invalid period.
3) LVDS timing follows the timing specifications of LVDS receiver IC: THC63LVDF84B(Thine).
4) In case of blanking time fluctuation, please satisfy following condition.
tVBn > tVBn-1 − 3(tH)
MITSUBISHI Confidential
(10/27)
AA121XH03_02_05_First
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AA121XH03.PDF ] | |
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