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What is HCC4517B?

This electronic component, produced by the manufacturer "STMicroelectronics", performs the same function as "DUAL 64-STAGE STATIC SHIFT REGISTER".


HCC4517B Datasheet PDF - STMicroelectronics

Part Number HCC4517B
Description DUAL 64-STAGE STATIC SHIFT REGISTER
Manufacturers STMicroelectronics 
Logo STMicroelectronics Logo 


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HCC/HCF4517B
DUAL 64-STAGE STATIC SHIFT REGISTER
. CLOCK FREQUENCY 12MHz (TYP.) AT VDD =
10V
. SCHMITT TRIGGER CLOCK INPUTS ALLOW
OPERATION WITH VERY SLOW CLOCK RISE
AND FALL TIMES
. THREE-STATE OUTPUTS
. QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
. STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
. 5V, 10V, AND 15V PARAMETRIC RATINGS
. INPUT CURREN OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD N°. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4517BF
HCF4517BM1
HCF4517BC1
PIN CONNECTIONS
DESCRIPTION
The HCC4517B (extended temperature range) and
HCF4517B (intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package.
The HCC/HCF4517B dual 64-stage static shift reg-
ister consists of two independent registers each
having a clock, data, and write enable input and out-
puts accessible at taps following the 16th, 32nd,
48th, and 64th stages. These taps also serve as
input points allowing data to be inputted at the 17th,
33rd, and 49th stages when the write enable input
is a logic 1 and the clock goes through a low-to-high
transition. The truth table indicates how the clock
and write enable inputs control the operation of the
HCC/HCF4517B. Inputs at the intermediate taps
allow entry of 64 bits into the register with 16 clock
pulses. The 3-state outputs permit connection of this
device to an external bus.
September 1988
1/12

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HCC4517B equivalent
HCC/HCF4517B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, Input tr, tf = 20ns, CL = 50pF,
RL = 200k)
Symbol
Parameter
tP HL , tP L H Propagation Delay Time :
CL to Bit 16 Tap
Test Conditions
V al ue
V D D (V) Min. Typ. Max.
5 200 400
10 110 220
15 90 180
Unit
ns
tPL Z, tP HZ 3-State Output WE to Bit 16 Tap
t PZ L , tP ZH (see note)
t THL , tT L H Output Transition Time
5 75 150
10
40 80
ns
15 30 60
5 100 200
10
50 100
ns
t se tu p Write Enable to Clock
15 40 80
5 – 100 – 50
10 – 50 – 25
15 – 30 – 15
ns
t se tu p Data to Clock
5 – 100 – 50
10 – 60 – 30
ns
Write Enable to Clock
Release Time
15 – 30 – 15
5 50 100
10 25 50
ns
15 20 40
t h o ld Data to Clock
5 100 200
10
50 100
ns
15 25 50
tW Minimum Clock Pulse Width
5 90 180
10
40 80
ns
15 25 50
fCL Maximum Clock Input
Frequency
5 36
10 6 12
MHz
tf, tr Maximum Clock Input Rise
or Fall Time
15 8 15
5
10 UNLIMITED
15
µs
Note : Measured at the point of 10% change in output load of 50pF, RL = 1kto VDD for tPZL, tPLZ and RL = 1kto VSS for tPHZ.
5/12


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