N25Q128A Datasheet PDF - Micron
Part Number | N25Q128A | |
Description | NOR Flash Memory | |
Manufacturers | Micron | |
Logo | ||
There is a preview and N25Q128A download ( pdf file ) link at the bottom of this page. Total 30 Pages |
Preview 1 page No Preview Available ! 128Mb, Multiple I/O Serial Flash Memory
Features
Micron Serial NOR Flash Memory
1.8V, Multiple I/O, 4KB Sector Erase
N25Q128A
Features
• SPI-compatible serial bus interface
• 108 MHz (MAX) clock frequency
• 1.7–2.0V single supply voltage
• Dual/quad I/O instruction provides increased
throughput up to 432 MHz
• Supported protocols
– Extended SPI, dual I/O, and quad I/O
• Execute-in-place (XIP) mode for all three protocols
– Configurable via volatile or nonvolatile registers
– Enables memory to work in XIP mode directly af-
ter power-on
• PROGRAM/ERASE SUSPEND operations
• Continuous read of entire memory via a single com-
mand
– Fast read
– Quad or dual output fast read
– Quad or dual I/O fast read
• Flexible to fit application
– Configurable number of dummy cycles
– Output buffer configurable
• Software reset
• 64-byte, user-lockable, one-time programmable
(OTP) dedicated area
• Erase capability
– Subsector erase 4KB uniform granularity blocks
– Sector erase 64KB uniform granularity blocks
– Full-chip erase
• Write protection
– Software write protection applicable to every
64KB sector via volatile lock bit
– Hardware write protection: protected area size
defined by five nonvolatile bits (BP0, BP1, BP2,
BP3, and TB)
– Additional smart protections, available upon re-
quest
• Electronic signature
– JEDEC-standard 2-byte signature (BB18h)
– Unique ID code (UID): 17 read-only bytes, in-
cluding:
• Two additional extended device ID (EDID)
bytes to identify device factory options
• Customized factory data (14 bytes)
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
• Packages JEDEC standard, all RoHS compliant
– F7 = V-PDFN-8 6mm x 5mm Sawn (MLP8 6mm x
5mm)
– F8 = V-PDFN-8 8mm x 6mm (MLP8 8mm x 6mm)
– 12 = T-PBGA-24b05 6mm x 8mm
– SF = SOP2-16 300 mils body width (SO16W)
– SE = SOP2-8 208 mils body width (SO8W)
PDF: 09005aef845665f6
n25q_128mb_1_8v_65nm.pdf - Rev. P 05/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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128Mb, Multiple I/O Serial Flash Memory
Features
List of Tables
Table 1: Signal Descriptions ........................................................................................................................... 10
Table 2: Sectors[255:0] ................................................................................................................................... 13
Table 3: Data Protection using Device Protocols ............................................................................................. 14
Table 4: Memory Sector Protection Truth Table .............................................................................................. 14
Table 5: Protected Area Sizes – Upper Area ..................................................................................................... 14
Table 6: Protected Area Sizes – Lower Area ...................................................................................................... 15
Table 7: SPI Modes ........................................................................................................................................ 17
Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................ 19
Table 9: Status Register Bit Definitions ........................................................................................................... 21
Table 10: Nonvolatile Configuration Register Bit Definitions ........................................................................... 22
Table 11: Volatile Configuration Register Bit Definitions .................................................................................. 23
Table 12: Sequence of Bytes During Wrap ....................................................................................................... 25
Table 13: Supported Clock Frequencies .......................................................................................................... 25
Table 14: Enhanced Volatile Configuration Register Bit Definitions .................................................................. 25
Table 15: Flag Status Register Bit Definitions .................................................................................................. 26
Table 16: Command Set ................................................................................................................................. 28
Table 17: Lock Register .................................................................................................................................. 33
Table 18: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands ....................................... 36
Table 19: Read ID Data Out ............................................................................................................................ 36
Table 20: Extended Device ID, First Byte ......................................................................................................... 36
Table 21: Serial Flash Discovery Parameter – Header Structure ........................................................................ 38
Table 22: Parameter ID .................................................................................................................................. 38
Table 23: Command/Address/Data Lines for READ MEMORY Commands ....................................................... 40
Table 24: Data/Address Lines for PROGRAM Commands ................................................................................ 44
Table 25: Suspend Parameters ....................................................................................................................... 54
Table 26: Operations Allowed/Disallowed During Device States ...................................................................... 55
Table 27: Reset Command Set ........................................................................................................................ 56
Table 28: OTP Control Byte (Byte 64) .............................................................................................................. 58
Table 29: XIP Confirmation Bit ....................................................................................................................... 61
Table 30: Effects of Running XIP in Different Protocols .................................................................................... 61
Table 31: Power-Up Timing and VWI Threshold ............................................................................................... 64
Table 32: AC RESET Conditions ...................................................................................................................... 65
Table 33: Absolute Ratings ............................................................................................................................. 70
Table 34: Operating Conditions ...................................................................................................................... 70
Table 35: Input/Output Capacitance .............................................................................................................. 70
Table 36: AC Timing Input/Output Conditions ............................................................................................... 71
Table 37: DC Current Characteristics and Operating Conditions ...................................................................... 72
Table 38: DC Voltage Characteristics and Operating Conditions ...................................................................... 72
Table 39: AC Characteristics and Operating Conditions ................................................................................... 73
Table 40: Part Number Information ................................................................................................................ 80
Table 41: Package Details ............................................................................................................................... 80
PDF: 09005aef845665f6
n25q_128mb_1_8v_65nm.pdf - Rev. P 05/14 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for N25Q128A electronic component. |
Information | Total 30 Pages | |
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