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PDF IC-706MKIIG Data sheet ( Hoja de datos )
| Número de pieza | IC-706MKIIG | |
| Descripción | HF/VHF/UHF ALL MODE TRANSCEVER Service Manual | |
| Fabricantes | Icom | |
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Hay una vista previa y un enlace de descarga de IC-706MKIIG (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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HF/VHF/UHF ALL MODE TRANSCEVER
S-14411XZ-C1
June. 2007
1 page  
SECTION 2
• MAIN AND FILTER BOARDS
INSIDE VIEWS
D/A converter
(IC2201: M62352GP)
RX preamplifier
(IC151: PC1658G)
HPF board
1st mixer
(D271: HSB88WSTR)
1st IF filter
(FI511: FI-261)
2nd mixer *
(D551: HSB88WSTR)
2nd IF filter
(FI561: FL-23)
Space for optional filters
⎛⎜⎝FFLL--120303,,
FL-101,
FL-232
FL-103⎞⎟⎠
• PA AND PLL UNITS
Power amplifers
(Q171, Q172, Q231: SRFJ7044)
DDS IC
(IC101: SC-1246)
BFO DDS IC
(IC901: SC-1287)
PLL IC *
(IC461: LMX2306TMX)
VCO1 *
(Q301: 2SK508)
VCO2 *
(Q331: 2SK508)
2-1
FILTER board
MAIN CPU clock
(X2161: CR-636)
MAIN CPU *
(IC 2001: HD6433337YA56F)
MAIN board
3rd IF filter for FM *
(FI791: SFPC455E-TC01)
MIC amplifier
(IC931: PC5023GS-077-E1)
AF selector switch *
(IC861: BU4052BCFV-E2)
Discriminator
(X791: CDB455CX24)
Balanced modulator *
(IC1041: NJM1496V)
FM IF IC *
(IC791: TA31136FN)
Tx FM PLL IC *
(IC1011: LC7153M-TLM)
PA unit
DRIVER board
Drive amplifers
(Q161, Q211: MRF1508TI)
Predrive amplifier
(Q101: 2SK2854)
Predrive amplifer
(Q121: MXR9745)
AF power amplifer
(IC231: LA4425A)
PLL unit
AF volume controller
(IC201: M5282FP)
VCO3 *
(Q361: 2SK508)
Reference oscillator
(X621: CR-275A 30.00000 MHz)
*Located under side of the point
5 Page 
The “FOR”, “VFOR” and “UFOR” voltages are combined to
the “FORL” voltage and then applied to IC1091b (pin 6). The
“POCV” voltage from the D/A converter (IC2201, pin 3),
determined by the RF power setting, is applied to IC1091b
(pin 5) as the reference voltage.
When the “FORL” voltage exceeds the “POCV” voltage, ALC
bias voltage from IC1091a (pin 1) controls the PIN diodes
(D521, D522, D572, D573) using Q1092. This adjusts the
output power to the level determined by the RF power set-
ting until the “FORL” and “POCV” voltages are equalized.
In AM mode, IC1091a operates as an averaging ALC ampli-
fier with Q1091 and C1091. Q1071 turns ON and the
“POCV” voltage is shifted for 40 W AM output power (maxi-
mum, 20 W for 144 MHz band, 8 W for 440 MHz band)
through R1080.
The ALC bias voltage from IC1091a is also applied to the
main CPU (IC2001 pin 34) as the “ALCL” voltage for ALC
meter indication.
An external ALC input (minus voltage) from the [ACC] sock-
et (pin 6) is shifted to plus voltage at D1131 and is applied
to the buffer amplifier (Q1131). External ALC operation is
identical to that of the internal ALC.
3-2-8 APC CIRCUIT (MAIN BOARD)
The APC (Automatic Power Control) circuit protects the
power amplifiers on the PA unit from high SWR and exces-
sive current for the HF/50 MHz band.
The reflected wave signal appears and increases on the
antenna connector when the antenna is mismatched. The
HF/50 MHz reflected signal level is detected at D10 (FILTER
board), and is amplified at the APC amplifier (IC1091c) and
applied to the ALC circuit as the reference voltage.
For the current APC, the driving current at the power ampli-
fier is detected in the voltages (“ICH” and “ICL”) which
appear at both terminals of a 0.012 Ω resistor (R201) on the
PA unit. The detected voltages are applied to the differential
amplifier (IC1091d, pins 13, 12). When the current of the
power amplifier exceeds 22 A, IC1091d controls the ALC
line via IC1091a to prevent excessive current flow.
3-2-9 RF, ALC, SWR METER CIRCUITS
(MAIN BOARD)
While transmitting, RF, ALC or SWR meter readings are
available and can be selected with the [MET] switch.
(1) Power meter
The “FOR”, “VFOR” and “UFOR” voltages are combined to
the “FORL” voltage, and it is then applied to the main CPU
(IC2001, pin 35) via the analog switch (IC2101, pins 11, 13)
for indicating the output power.
(2) ALC meter
The ALC bias voltage from IC1091a pin 1 is applied to the
main CPU (IC2001, pin 34) via the “ALCV” signal line for
indicating the ALC level.
(3) SWR meter
The “FORL” and “REFL” voltages are applied to the main
CPU (IC2001, pins 32 and 36) via the analog switch
(IC2101, pins 11, 13 and 4, 3) respectively. The main CPU
compares the ratio of “FORV” to “REFV” voltage and indi-
cates the SWR for the [ANT1] connector.
3-3 PLL CIRCUITS
3-3-1 GENERAL
The PLL unit generates a 1st LO frequency
(69.0415–530.0115 MHz), a 2nd LO frequency (60 MHz), a
BFO frequency (9.01 MHz), an FM 3rd LO frequency
(9.4665/9.4650 MHz) and a TX FM PLL reference frequen-
cy (9.0115/9.0100 MHz).
The 1st LO PLL adopts a mixer-less dual loop PLL system
and has 3 VCO circuits. The BFO uses a DDS and the 2nd
LO uses a fixed frequency double that of the crystal oscilla-
tor.
3-3-2 1ST LO PLL CIRCUIT
The 1st LO PLL contains a main loop and reference loop
forming a dual loop system.
The reference loop generates a 10.6605 to 10.683 MHz fre-
quency using a DDS circuit, and the main loop generates a
69.0415 to 269.50575 MHz frequency using the reference
loop frequency.
While operating on 60 MHz and above, the output is doubled
at D531 for oscillating a wide frequency range.
(1) REFERENCE LOOP PLL
The oscillated signal at the reference VCO (Q1, D1) is
amplified at the amplifiers (Q21, Q51) and is then applied to
the DDS IC (IC101, pin 46). The signal is then divided and
detected on phase with the DDS generated frequency.
The detected signals output from IC101 (pin 56) is convert-
ed into a DC voltage (lock voltage) at the loop filter (R133,
R134, C133) and then fed back to the varactor diode (D1) in
the VCO circuit.
(2) MAIN LOOP PLL
The oscillated signal at one of the main loop VCOs (Q301,
Q331, Q361) is amplified at the buffer amplifiers (Q10) and
is then applied to the PLL IC (IC461, pin 6). The signal is
then divided and detected on phase with the reference loop
output frequency.
The detected signal output from the PLL IC (IC461, pin 2) is
converted into a DC voltage (lock voltage) at the active loop
filter and then fed back to one of the varactor diodes (D301,
D331, D361) in the VCO circuits. While operating on 60 MHz
and above, the VCO output is doubled at the doubler circuit
(D531) and amplified at the ampolifier (IC541).
The oscillated signal passes through a low-pass or band-
pass filter and is then applied to the MAIN board as a 1st LO
signal.
3-6
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