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PDF HD-4702 Data sheet ( Hoja de datos )
| Número de pieza | HD-4702 | |
| Descripción | CMOS Programmable Bit Rate Generator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HD-4702/883
June 1998
CMOS Programmable Bit Rate Generator
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1. 2. 1.
• HD-4702/883 Provides 13 Commonly Used Bit Rates
• Uses a 2.4576MHz Crystal/Input for Standard
Frequency Output (16 Times Bit Rate)
• Low Power Dissipation
• Conforms to ElA RS-404
• One HD-4702/883 Controls up to Eight Transmission
Channels
• Initialization Circuit Facilitates Diagnostic Fault
Isolation
• On-Chip Input Pull-Up Circuit
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE (oC) PACKAGE
PKG. NO.
HD1-4702/883
-55 to 125 CERDIP F16.3
Description
The HD-4702/883 Bit Rate Generator provides the
necessary clock signals for digital data transmission sys-
tems, such as a UART. It generates 13 commonly used bit
rates using an on-chip crystal oscillator or an external input.
For conventional operation generating 16 output clock
pulses per bit period, the input clock frequency must be
2.4576MHz (i.e., 9600 Baud x 16 x 16, since there is an
internal ÷ 16 prescaler). A lower input frequency will result in
a proportionally lower output frequency.
The HD-4702/883 can provide multi-channel operation with
a minimum of external logic by having the clock frequency
CO and the ÷ 8 prescaler outputs Q0, Q1, Q2 available
externally. All signals have a 50% duty cycle except 1800
Baud, which has less than 0.39% distortion.
The four rate select inputs (S0-S3) select which bit rate is at
the output (Z). See Truth Table for Rate Select Inputs for
select code and output bit rate. Two of the 16 select codes
for the HD-4702/883 do not select an internally generated
frequency, but select an input into which the user can feed
either a different frequency, or a static level (High or Low) to
generate “ZERO BAUD”.
The bit rates most commonly used in modern data terminals
(110,150, 300,1200, 2400 Baud) require that no more than
one input be grounded for the HD-4702/883, which is easily
achieved with a single 5-position switch.
The HD-4702/883 has an initialization circuit which
generates a master reset for the scan counter. This signal is
derived from a digital differentiator that senses the first high
level on the CP input after the ECP input goes low. When
ECP is high, selecting the crystal input, CP must be low. A
high level on CP would apply a continuous reset. See Clock
Modes and Initialization below.
Pinout
HD-4702/883 (CERDIP)
TOP VIEW
Q0
Q1
Q2
ECP
CP
OX
IX
GND
1
2
3
4
5
6
7
8
16 VCC
15 IM
14 S0
13 S1
12 S2
11 S3
10 Z
9 CO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 2955.2
1 page  
HD-4702/883
AC PARAMETER
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
SYMBOL
CONDITIONS NOTES TEMPERATURE (oC)
MIN
MAX UNITS
Input Capacitance
Output Capacitance
CIN All Measurements
are referenced to
CO device ground,
f = 1MHz.
10
10
TA = 25
TA = 25
- 7.0 pF
- 15.0 pF
Propagation Delay IX to CO
tPLH
10, 12
-55 ≤ TA ≤ 125
- 300 ns
Propagation Delay IX to CO
tPHL
10, 12
-55 ≤ TA ≤ 125
- 250 ns
Propagation Delay CP to CO
tPLH
10, 12
-55 ≤ TA ≤ 125
- 215 ns
Propagation Delay CP to CO
tPHL
10, 12
-55 ≤ TA ≤ 125
- 195 ns
Propagation Delay CO to Qn
Propagation Delay CO to Qn
tPLH
tPHL
VCC = 4.5V
CL ≤ 7pF on OX
CL = 15pF
10, 12
10, 12
-55 ≤ TA ≤ 125
-55 ≤ TA ≤ 125
- (Note 11) ns
- (Note 11) ns
Propagation Delay CO to Z
tPLH
10, 12
-55 ≤ TA ≤ 125
-
75 ns
Propagation Delay CO to Z
tPHL
10, 12
-55 ≤ TA ≤ 125
-
65 ns
Output Transition Time (Except OX)
tTLH
10, 12
-55 ≤ TA ≤ 125
-
80 ns
Output Transition Time (Except OX)
tTHL
10, 12
-55 ≤ TA ≤ 125
-
40 ns
NOTES:
10. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design and after major process and/or design changes.
11. For multichannel operation, Propagation Delay (CO to Qn) plus Set-Up Time, Select to CO, is guaranteed to be ≤ 367ns.
12. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL).
Set-Up Times (tS), Hold Times (tH), and Minimum Pulse Widths (tW) do not vary with load capacitance.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
Interim Test
PDA
Final Test
Group A
Groups C and D
METHOD
100%/5004
100%/5004
100%
100%
-
Samples/5005
SUBGROUPS
-
1, 7, 9
1
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
5
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