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PDF HD-15530 Data sheet ( Hoja de datos )
| Número de pieza | HD-15530 | |
| Descripción | CMOS Manchester Encoder-Decoder | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HD-15530
March 1997
CMOS Manchester Encoder-Decoder
Features
Description
• Support of MlL-STD-1553
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
CERDIP
SMD#
CLCC
SMD#
PDIP
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
1.25 MEGABIT/s
HD1-15530-9
HD1-15530-8
7802901JA
HD4-15530-9
HD4-15530-8
78029013A
HD3-15530-9
PKG. NO.
F24.6
J28.A
E24.6
The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections
operate completely independent of each other, except for
the Master Reset functions.
This circuit meets many of the requirements of MIL-STD-
1553. The Encoder produces the sync pulse and the parity
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decod-
ing the data bits and checking parity.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MlL-STD-1553 over both temperature and
voltage. It interfaces with CMOS, TTL or N channel support
circuitry, and uses a standard 5V supply.
The HD-15530 can also be used in many party line digital
data communications applications, such as an environmen-
tal control system driven from a single twisted pair cable of
fiber optic cable throughout the building.
Pinouts
HD-15530 (CERDIP, PDIP)
TOP VIEW
VALID WORD 1
ENCODER
SHIFT CLK
2
TAKE DATA 3
SERIAL DATA OUT 4
DECODER CLK 5
BIPOLAR ZERO IN 6
BIPOLAR ONE IN 7
UNIPOLAR DATA IN 8
DECODER SHIFT CLK 9
COMMAND/
DATA SYNC
10
DECODER RESET 11
GND 12
24 VCC
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15
BIPOLAR
ZERO OUT
14 ÷ 6 OUT
13 MASTER RESET
HD-15530 (CLCC)
TOP VIEW
4 3 2 1 28 27 26
DECODER
CLK
5
25
SEND
DATA
NC 6
24 NC
NC 7
23 NC
BIPOLAR
ZERO IN
8
22
SYNC
SELECT
BIPOLAR
ONE IN
9
21
ENCODER
ENABLE
UNIPOLAR
DATA IN
10
20
SERIAL
DATA IN
DECODER
SHIFT CLK
11
19
BIPOLAR
ONE OUT
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
142
FN2960.1
1 page  
HD-15530
How to Make Our MTU Look Like a Manchester Encoded UART
VALID WORD
DECODER
ENCODER CLK
BIPOLAR
ZERO IN
BIPOLAR
ONE IN
UNIPOLAR
DATA IN
COMMAND
SYNC
DECODER
RESET
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
VCC
SYNC
SELECT
ENCODER
ENABLE
BIPOLAR
ONE OUT
INHIBIT
OUTPUT
BIPOLAR
ZERO OUT
MASTER
RESET
A B CK H A B CK
74LS164
74LS164
PARALLEL OUT
FIGURE 3.
OH SH/LD CK SI OH SH/LD CK
74165
74165
PARALLEL IN
Typical Timing Diagrams for a Manchester Encoded UART
ENCODER ENABLE
SYNC SELECT
VALID
PARALLEL IN
BIPOLAR ONE OUT
P
BIPOLAR ZERO OUT
SYNC
MSB
P
LSB PARITY
FIGURE 4. ENCODER TIMING
VALID
BIPOLAR ONE IN
SYNC
BIPOLAR ZERO IN
COMMAND SYNC
PARALLEL OUT
VALID
VALID WORD
FROM
PREVIOUS
RECEPTION
MSB
LSB PARITY
P
P
FIGURE 5. DECODER TIMING
146
VALID
5 Page 
HD-15530
Timing Waveforms (Continued)
BIPOLAR ONE IN
BIPOLAR ZERO IN
BIPOLAR ONE IN
BIPOLAR ZERO IN
BIPOLAR ONE IN
BIPOLAR ZERO IN
NOTE: UNIPOLAR IN = 0, FOR NEXT DIAGRAMS.
BIT PERIOD
TD1
TD2
COMMAND SYNC
BIT PERIOD
TD3
TD1
BIT PERIOD
TD2
TD1
TD2
DATA SYNC
TD1
TD3 TD3
TD1
TD4
ONE
TD5
TD1 TD3
TD3
TD1
TD2
TD3
ZERO
TD5
TD3
TD1
TD4
ONE
UNIPOLAR IN
UNIPOLAR IN
UNIPOLAR IN
NOTE: BIPOLAR ONE IN = 0; BIPOLAR ZERO IN = 1, FOR NEXT DIAGRAMS.
TD2
COMMAND SYNC
TD2
DATA SYNC
TD4
TD5
ONE
ZERO
TD2
TD2
TD5 TD4
ONE
TD3
TD3
TD4
ONE
Test Load Circuit
DUT
CL9
(NOTE)
NOTE: Includes stray and jig capacitance.
FIGURE 12. DECODER TIMING
AC Testing Input, Output Waveform
INPUT
VIH
OUTPUT
VOH
50%
50%
VIL VOL
AC Testing: All input signals must switch between VIL and VIH.
Input rise and fall times are driven at 1ns per volt.
152
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HD-15530.PDF ] | |
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