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PDF HCTS10K Data sheet ( Hoja de datos )
| Número de pieza | HCTS10K | |
| Descripción | Radiation Hardened Triple 3-Input NAND Gate | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HCTS10MS
September 1995
Radiation Hardened
Triple 3-Input NAND Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
A2 3
B2 4
14 VCC
13 C1
12 Y1
11 C3
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
C2 5
Y2 6
GND 7
10 B3
9 A3
8 Y3
• DC Operating Voltage Range: 4.5V to 5.5V
- LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS10MS is a Radiation Hardened Triple 3-Input
NAND Gate. A high on all inputs forces the output to a Low state.
The HCTS10MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
A2
B2
C2
Y2
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
C1
Y1
C3
B3
A3
Y3
Functional Diagram
The HCTS10MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCTS10DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP
S Equivalent
HCTS10KMSR -55oC to +125oC Intersil Class 14 Lead Ceramic
S Equivalent Flatpack
HCTS10D/
Sample
+25oC
Sample
14 Lead SBDIP
HCTS10K/
Sample
+25oC
Sample
14 Lead Ceramic
Flatpack
HCTS10HMSR
+25oC
Die
Die
An
(1, 3, 9)
Bn
(2, 4, 10)
Cn
(5, 11, 13)
Yn
(6, 8, 12)
TRUTH TABLE
INPUTS
OUTPUTS
An Bn Cn
Yn
LLL
H
L LH
H
LHL
H
L HH
H
HL L
H
HLH
H
HH L
H
HHH
L
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518778
File Number 2434.2
1 page  
Specifications HCTS10MS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V
50kHz
25kHz
STATIC BURN-IN I TEST CONDITIONS (Note 1)
6, 8, 12
1, 2, 3, 4, 5, 7, 9, 10, 11,
13
-
14 - -
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
6, 8, 12
7
-
1, 2, 3, 4, 5, 9, 10,
-
11, 13, 14
-
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
-
7
6, 8, 12
14
1, 2, 3, 4, 5, 9,
-
10, 11, 13
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
6, 8, 12
7 1, 2, 3, 4, 5, 9, 10, 11, 13, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518778
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HCTS10K.PDF ] | |
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