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What is AT25DN256-MAHFGP-T?

This electronic component, produced by the manufacturer "Adesto", performs the same function as "2.3V Minimum SPI Serial Flash Memory".


AT25DN256-MAHFGP-T Datasheet PDF - Adesto

Part Number AT25DN256-MAHFGP-T
Description 2.3V Minimum SPI Serial Flash Memory
Manufacturers Adesto 
Logo Adesto Logo 


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AT25DN256
256-Kbit, 2.3V Minimum
SPI Serial Flash Memory with Dual-Read Support
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
40ms Typical 4-Kbyte Block Erase Time
320ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
350nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
6mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6mm)
8-lead TSSOP Package
DS-25DN256–039B–5/2014

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AT25DN256-MAHFGP-T equivalent
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DN256 can be erased in three levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
Figure 4-1. Memory Architecture Diagram
Block Erase Detail
32KB
4KB
Block Erase
Block Erase
(52h Command) (20h Command)
Block Address
Range
32KB
4KB 007FFFh – 007000h
4KB 006FFFh – 006000h
4KB 005FFFh – 005000h
4KB 004FFFh – 004000h
4KB 003FFFh – 003000h
4KB 002FFFh – 002000h
4KB 001FFFh – 001000h
4KB 000FFFh – 000000h
Page Program Detail
1-256 Byte
Page Program
(02h Command)
256 Bytes
256 Bytes
256 Bytes
Page Address
Range
007FFFh – 007F00h
007EFFh – 007E00h
007DFFh – 007D00h
256 Bytes
256 Bytes
256 Bytes
0002FFh – 000200h
0001FFh – 000100h
0000FFh – 000000h
5. Device Operation
The AT25DN256 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the
SPI Master. The SPI Master communicates with the AT25DN256 via the SPI bus which is comprised of four signal lines:
Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DN256
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
Figure 5-1. SPI Mode 0 and 3
CS
SCK
SI MSB
LSB
SO
MSB
LSB
5.1 Dual Output Read
The ATx features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every clock cycle
to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of data bytes.
With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.
AT25DN256
DS-25DN256–039B–5/2014
5


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Featured Datasheets

Part NumberDescriptionMFRS
AT25DN256-MAHFGP-TThe function is 2.3V Minimum SPI Serial Flash Memory. AdestoAdesto

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