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PDF AX1250ES Data sheet ( Hoja de datos )
| Número de pieza | AX1250ES | |
| Descripción | 2A Sink/Source Bus Termination Regulator | |
| Fabricantes | AXElite | |
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Hay una vista previa y un enlace de descarga de AX1250ES (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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AX1250ES
2A Sink/Source Bus Termination Regulator
GENERAL DESCRIPTION
The AX1250ES is a simple, cost-effective and high-speed linear regulator designed
to generate termination voltage in double data rate (DDR) memory system to comply with
the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and
SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing
up to 2A while regulating an output voltage to within 40mV. The output termination voltage
cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the
desired output voltage can be programmed by externally forcing the REFEN pin voltage.
The AX1250ES also incorporates a high-speed differential amplifier to provide
ultra-fast response in line/load transient. Other features include extremely low initial offset
voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal
shut-down protection.
The AX1250ES are available in the SOP-8L-EP (Exposed Pad) surface mount
packages.
FEATURES
- Ideal for DDR-I, DDR-II and DDR-III VTT Applications
- Sink and Source 2A Continuous Current
- Integrated Power MOSFETs
- Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3
Interfaces.
- High Accuracy Output Voltage at Full-Load
- Output Voltage traces REFEN Pin Voltage.
- Low External Component Count
- Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output
- Current Limiting Protection
- Thermal Shutdown Protection
- SOP-8L with exposed pad Pb-Free Package.
1/9
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Aug.24, 2011
1 page  
AX1250ES
Thermal Considerations
The AX1250ES series can deliver a current of up to 2A over the full operating
junction temperature range. However, the maximum output current must be dated at
higher ambient temperature to ensure the junction temperature does not exceed 125°C.
With all possible conditions, the junction temperature must be within the range specified
under operating conditions. Power dissipation can be calculated based on the output
current and the voltage drop across regulator.
PD = (VIN - VOUT) × IOUT+ VIN × IQ
The final operating junction temperature for any set of conditions can be estimated
by the following thermal equation:
PD (MAX) = (TJ (MAX) - TA) / θJA
Where TJ (MAX) is the maximum junction temperature of the die (125°C) and TA is the
maximum ambient temperature. The junction to ambient thermal resistance (θJA) for
SOP-8L-EP (Exposed pad) package at recommended minimum footprint is 40°C/W on 1.5
in2 and Multi-layer PCB layout. The maximum power dissipation at TA = 25°C can be
calculated by following formula:
PD (MAX) = (125°C - 25°C) / 40°C/W = 2.5W
The thermal resistance θJA of SOP-8L-EP (Exposed Pad) is determined by the
package design and the PCB design. However, the package design has been decided. If
possible, it's useful to increase thermal performance by the PCB design. The thermal
resistance can be decreased by adding copper under the expose pad of SOP-8L-EP
package. We have to consider the copper couldn't stretch infinitely and avoid the tin
overflow.
5/9
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Aug.24, 2011
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet AX1250ES.PDF ] | |
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