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PDF MAX19700 Data sheet ( Hoja de datos )

Número de pieza MAX19700
Descripción Ultra-Low-Power Analog Front-End
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo




1. MAX19700






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19-3826; Rev 1; 6/07
EVAALVUAAILTAIOBNLEKIT
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
General Description
The MAX19707 is an ultra-low-power, mixed-signal ana-
log front-end (AFE) designed for power-sensitive com-
munication equipment. Optimized for high dynamic
performance at ultra-low power, the device integrates a
dual, 10-bit, 45Msps receive (Rx) ADC; dual, 10-bit,
45Msps transmit (Tx) DAC; three fast-settling 12-bit
aux-DAC channels for ancillary RF front-end control;
and a 10-bit, 333ksps housekeeping aux-ADC. The typ-
ical operating power in Tx-Rx FAST mode is 84.6mW at
a 45MHz clock frequency.
The Rx ADCs feature 54.2dB SNR and 71.2dBc SFDR
at fIN = 5.5MHz and fCLK = 45MHz. The analog I/Q
input amplifiers are fully differential and accept
1.024VP-P full-scale signals. Typical I/Q channel match-
ing is ±0.03° phase and ±0.01dB gain.
The Tx DACs feature 73.2dBc SFDR at fOUT = 2.2MHz
and fCLK = 45MHz. The analog I/Q full-scale output volt-
age is ±400mV differential. The Tx DAC common-mode
DC level is programmable from 0.71V to 1.05V. The I/Q
channel offset is programmable to optimize radio lineup
sideband/carrier suppresion. The typical I/Q channel
matching is ±0.01dB gain and ±0.07° phase.
The Rx ADC and Tx DAC share a single, 10-bit parallel,
high-speed digital bus allowing half-duplex operation
for time-division duplex (TDD) applications. A 3-wire
serial interface controls power-management modes, the
aux-DAC channels, and the aux-ADC channels.
The MAX19707 operates on a single 2.7V to 3.3V ana-
log supply and 1.8V to 3.3V digital I/O supply. The
MAX19707 is specified for the extended (-40°C to
+85°C) temperature range and is available in a 48-pin,
thin QFN package. The Selector Guide at the end of the
data sheet lists other pin-compatible versions in this
AFE family.
Applications
WiMAX CPEs
VoIP Terminals
802.11a/b/g WLAN
Portable Communication
Equipment
Ordering Information
PART*
PIN-PACKAGE
PKG CODE
MAX19707ETM
48 Thin QFN-EP**
T4877-4
MAX19707ETM+ 48 Thin QFN-EP**
T4877-4
*All devices are specified over the -40°C to +85°C operating
range.
**EP = Exposed paddle.
+Denotes lead-free package.
Features
Dual, 10-Bit, 45Msps Rx ADC and Dual, 10-Bit,
45Msps Tx DAC
Ultra-Low Power
84.6mW at fCLK = 45MHz, Fast Mode
77.1mW at fCLK = 45MHz, Slow Mode
Low-Current Standby and Shutdown Modes
Programmable Tx DAC Common-Mode DC Level
and I/Q Offset Trim
Excellent Dynamic Performance
SNR = 54.2dB at fIN = 5.5MHz (Rx ADC)
SFDR = 73.2dBc at fOUT = 2.2MHz (Tx DAC)
Three 12-Bit, 1µs Aux-DACs
10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and
Data Averaging
Excellent Gain/Phase Match
±0.03° Phase, ±0.01dB Gain (Rx ADC) at
fIN = 5.5MHz
Multiplexed Parallel Digital I/O
Serial-Interface Control
Versatile Power-Control Circuits
Shutdown, Standby, Idle, Tx/Rx Disable
Miniature 48-Pin Thin QFN Package
(7mm x 7mm x 0.8mm)
Pin Configuration
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25
DAC2
DAC1
VDD
IDN
IDP
GND
VDD
QDN
QDP
REFIN
COM
REFN
37
38
39
40
41
42
43
44
45
46
47
48
MAX19707
EXPOSED PADDLE (GND)
24 D9
23 D8
22 D7
21 D6
20 OVDD
19 OGND
18 D5
17 D4
16 D3
15 D2
14 D1
13 D0
1 2 3 4 5 6 7 8 9 10 11 12
THIN QFN
Functional Diagram and Selector Guide appear at end of
data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX19700 pdf
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
Tx DAC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Residual DC Offset
SYMBOL
N
INL
DNL
VOS
Full-Scale Gain Error
Tx DAC DYNAMIC PERFORMANCE
DAC Conversion Rate
In-Band Noise Density
Third-Order Intermodulation
Distortion
Glitch Impulse
fCLK
ND
IM3
CONDITIONS
Guaranteed monotonic (Note 6)
TA +25°C
TA < +25°C
Include reference error TA +25°C
(peak-to-peak error) TA < +25°C
(Note 2)
fOUT = 2.2MHz, fCLK = 45MHz
f1 = 2MHz, f2 = 2.2MHz
MIN TYP MAX UNITS
10 Bits
±0.3
LSB
-1 ±0.2 +1 LSB
-4 ±1 +4
mV
-4.5 ±1 +4.5
-30 +30
mV
-40 +40
45 MHz
-130.6
dBc/Hz
80 dBc
10 pVs
Spurious-Free Dynamic Range to
Nyquist
SFDR fCLK = 45MHz, fOUT = 2.2MHz
60 73.2
dBc
Total Harmonic Distortion to
Nyquist
THD
fCLK = 45MHz, fOUT = 2.2MHz
-71 -59
dB
Signal-to-Noise Ratio to Nyquist
SNR
fCLK = 45MHz, fOUT = 2.2MHz
Tx DAC INTERCHANNEL CHARACTERISTICS
I-to-Q Output Isolation
Gain Mismatch Between DAC
Outputs
fOUTX,Y = 2MHz, fOUTX,Y = 2.2MHz
Measured at DC
TA +25°C
TA < +25°C
Phase Mismatch Between DAC
Outputs
fOUT = 2.2MHz, fCLK = 45MHz
Differential Output Impedance
Tx DAC ANALOG OUTPUT
Full-Scale Output Voltage
VFS
Bits CM1 = 0, CM0 = 0 (default)
Output Common-Mode Voltage
VCOM
Bits CM1 = 0, CM0 = 1
Bits CM1 = 1, CM0 = 0
Bits CM1 = 1, CM0 = 1
57.1 dB
-0.3
-0.42
85
±0.01
+0.3
+0.42
dB
dB
±0.07
Degrees
800
±400
1.0 1.05 1.1
0.95
0.80
0.71
mV
V
_______________________________________________________________________________________ 5

5 Page





MAX19700 arduino
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33µF, TA = +25°C, unless otherwise noted.)
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT AMPLITUDE
60
fIN = 13.00155MHz
QA
50
40
IA
30
20
10
0
-21
-18 -15 -12 -9 -6 -3
ANALOG INPUT AMPLITUDE (dBFS)
0
Rx ADC SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
56
fIN = 12.4980346MHz
IA
55
54
QA
53
52
5 10 15 20 25 30 35 40 45
SAMPLING RATE (MHz)
Rx ADC SPURIOUS-FREE DYNAMIC
RANGE vs. SAMPLING RATE
90
fIN = 12.4980346MHz
85
IA
80
75
70
QA
65
Rx ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT AMPLITUDE
-40
fIN = 12.4980346MHz
-45
-50
-55
-60 QA
-65
-70
-75
-80
-21
IA
-18 -15 -12 -9 -6 -3
ANALOG INPUT AMPLITUDE (dBFS)
0
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. SAMPLING RATE
57
fIN = 12.4980346MHz
56
IA
55
54
QA
53
52
5 10 15 20 25 30 35 40 45
SAMPLING RATE (MHz)
Rx ADC SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
57
fIN = 12.4980346MHz
56
55 QA
54
IA
53
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT AMPLITUDE
75
fIN = 12.4980346MHz
70
65 QA
60
55
IA
50
45
-21
-18 -15 -12 -9 -6 -3
ANALOG INPUT AMPLITUDE (dBFS)
0
Rx ADC TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
-55
fIN = 12.4980346MHz
-60
-65 QA
-70
-75
-80
IA
-85
-90
-95
5 10 15 20 25 30 35 40 45
SAMPLING RATE (MHz)
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. CLOCK DUTY CYCLE
57
fIN = 12.4980346MHz
56
55 QA
54
IA
53
60
5 10 15 20 25 30 35 40 45
SAMPLING RATE (MHz)
52
35
45 55
CLOCK DUTY CYCLE (%)
65
52
35
45 55
CLOCK DUTY CYCLE (%)
65
______________________________________________________________________________________ 11

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