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PDF LM5015MHX Data sheet ( Hoja de datos )

Número de pieza LM5015MHX
Descripción High Voltage Monolithic Two-Switch Forward DC-DC Regulator
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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December 10, 2007
LM5015
High Voltage Monolithic Two-Switch Forward DC-DC
Regulator
General Description
The LM5015 high voltage switch mode regulator features all
the functions necessary to implement efficient high voltage
Two-Switch Forward and Two-Switch Flyback regulators, us-
ing a minimum of external components. This easy to use
regulator integrates high side and low side 75 Volt N-Channel
MOSFETs with a minimum 1 Amp peak current limit. The
voltage across the MOSFETs employed in the two-switch
topology is clamped to the input voltage, allowing the input
voltage range to approach the rating of the MOSFETs. The
regulator control method is based on current mode control
providing inherent ease of loop compensation and line feed-
forward for superior rejection of input transients.
The operating frequency is set with a single resistor and is
programmable up to 750 kHz. The oscillator can also be syn-
chronized to an external clock. Additional protection features
include cycle-by-cycle current limiting, thermal shutdown, un-
der-voltage lockout and remote shutdown capability. The de-
vice is available in the TSSOP-14EP package featuring an
exposed die attach pad to enhance thermal dissipation.
Features
Dual Integrated 75V N-Channel MOSFETs
Ultra-wide input voltage range: 4.25V to 75V
Integrated high voltage bias regulator
Adjustable output voltage
1.5% feedback reference accuracy
Current mode control with selectable compensation
Wide bandwidth error amplifier
Integrated current sensing and limiting
50% maximum duty cycle limit
Single resistor oscillator programming
Oscillator synchronization capability
Programmable soft-start
Enable / Under-voltage Lockout (UVLO) pin
Thermal shutdown
Package
TSSOP-14EP (Exposed Pad)
Typical Application Schematic
© 2007 National Semiconductor Corporation 300346
30034601
www.national.com

1 page




LM5015MHX pdf
Symbol
Parameters
PWM COMPARATOR
Maximum Duty Cycle
Min On-time
Min On-time
VCOMP-OS
COMP to PWM Comparator
Offset
ERROR AMPLIFIER
VFB-REF
Feedback Reference Voltage
FB Bias Current
DC Gain
COMP Sink Current
COMP Short Circuit Current
COMP Open Circuit Voltage
COMP to SW Delay
Unity Gain Bandwidth
SOFT START
Soft-start Current Source
Soft-start to COMP Offset
THERMAL SHUTDOWN
TSD Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
THERMAL RESISTANCE
θJC Junction to Case
θJA Junction to Ambient
Conditions
VCOMP > VCOMP-OS
VCOMP < VCOMP-OS
Internal reference, VFB = VCOMP
VCOMP = 250mV
VFB = 0, VCOMP = 0
VFB = 0
Min Typ Max Units
49 %
140 ns
0 ns
0.9 1.3 1.55 V
1.236
2
0.9
4.5
1.26 1.274
10
72
1.2 1.5
5.15 5.95
50
4
V
nA
dB
mA
mA
V
ns
MHz
8 11 14 µA
0.3 0.5 0.7
V
165 °C
25 °C
6.6 °C/W
40 °C/W
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100pF capacitor discharged through a 1.5 kresistor into each pin. Test Method is per JESD-22-A114.
Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
5 www.national.com

5 Page





LM5015MHX arduino
FIGURE 3. Type II Compensator
30034618
When isolation between primary and secondary circuits is re-
quired, the Error Amplifier is usually disabled by connecting
the FB pin to AGND. This allows the COMP pin to be driven
directly by the collector of an opto-coupler. In isolated designs
the error amplifier is located on the secondary circuit and
drives the opto-coupler LED. The compensation network is
connected to the secondary side error amplifier. An example
of an isolated regulator with an opto-coupler is shown in Fig-
ure 13.
Current Sense Amplifier
The LM5015 employs peak current mode control which also
provides a cycle-by-cycle over current protection feature. An
internal 42 milli-Ohm current sense resistor measures the
current in the low side power MOSFET source. The sense
resistor voltage is amplified 30 times to provide a 1.25V/A
signal into the current limit comparator. Current limiting is ini-
tiated if the internal current limit comparator input exceeds the
1.5V threshold, corresponding to 1.2A. When the current limit
comparator is triggered, the HO and LO output pins immedi-
ately switches to the high impedance state.
The current sense signal provides the PWM comparator with
a control signal that reaches 1.5V when the MOSFET current
is 1.2A. To prevent erratic operation at low duty cycle, a lead-
ing edge blanking circuit attenuates the current sense signal
for 100 ns when the power MOSFET is turned on. When the
MOSFET is initially turned on, current spikes from the power
MOSFET drain-source and gate-source capacitances flow
through the current sense resistor. These transient currents
normally cease within 50 ns with proper selection of rectifier
diodes and proper PC board layout.
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the
IC in the event the maximum junction temperature is exceed-
ed. When the 165°C junction temperature threshold is
reached, the regulator is forced into a low power standby
state, disabling all functions except the VCC regulator. Ther-
mal hysteresis allows the IC to cool down by 25°C before it is
re-enabled.
Power MOSFETs
The LM5015 switching regulator includes two N-Channel
MOSFETs each with 450 mnominal on-resistance. The
drain of the high side MOSFET is the PVIN pin, and the source
the HO pin. The drain of the low side MOSFET is the LO pin,
and the source is internally connected to the PGND pin via
the 42 minternal current sense resistor. The on-resistance
of the LM5015 MOSFETs varies with temperature as shown
in the Typical Performance Characteristics graph. The typical
gate charge for each MOSFETs is 4.5 nC which is supplied
from the VCC and BST pins, respectively, when the MOS-
FETs are turned on.
The maximum duty cycle of the power MOSFETs is limited
less than 50%. This is achieved by an oscillator divide-by-two
circuit with an additional 50 ns of forced off-time introduced
between the CLK and RS Flip-Flop. Consequently, the max-
imum duty cycle is limited by the following equation:
DutyMax_Limit=(0.5 - 50 ns x FSW) x 100%
Where FSW is the switching frequency in Hertz (Hz). The pur-
pose of limiting the maximum duty cycle less than 50% is to
guarantee successful reset of the power transformer in the
Two-Switch Forward converter topology. See applications in-
formation below for more detail.
11 www.national.com

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